DS1743-85IND+ Maxim Integrated Products, DS1743-85IND+ Datasheet
DS1743-85IND+
Specifications of DS1743-85IND+
Related parts for DS1743-85IND+
DS1743-85IND+ Summary of contents
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... CE2 A11 A10 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 28-Pin Encapsulated Package (28 PIN 740 DS1743P GND BAT 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) : 090407 REV N.C. N.C. N.C. N.C. A12 A11 A10 A9 A8 ...
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... DQ0 12 15 DQ1 13 14 DQ2 14 17 GND 15 13 DQ3 16 12 DQ4 17 11 DQ5 18 10 DQ6 19 9 DQ7 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs FUNCTION PDIP No Connection Address Input Data Input/ Output — Ground — Data Input/ — Output PIN NAME FUNCTION PowerCap ...
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... The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its own power- fail circuitry, which deselects the device when the V ...
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... CLOCK OPERATIONS-READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. ...
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... As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit like the read bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit then transfers those values to the actual clock counters and allows normal operation to resume ...
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... Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM ...
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... WRITING DATA TO RAM OR CLOCK The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the cycle must return inactive for a minimum of t cycle. Data in must be valid t application, the OE signal will be high during a write cycle ...
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... Output Leakage Current (Any Output) Output Logic 1 Voltage (I = -1.0mA) OUT Output Logic 0 Voltage (I = 2.1mA) OUT Write-Protection Voltage Battery Switchover Voltage DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs TEMP RANGE 3.3V 10 10% 0°C to +70°C 3.3V 10 10% -40C to +85C SYMBOL CONDITIONS = 5V 10 ...
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... Over the Operating Range PARAMETER SYMBOL Read Cycle Time Address Access Time CE to CE2 to DQ Low-Z CE Access Time CE2 Access Time CE and CE2 Data-Off Time Low-Z OE Access Time OE Data-Off Time Output Hold from Address DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN CC1 I CC2 ...
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... Address Access Time CE and CE2 Low to DQ Low-Z CE and CE2 Access Time CE and CE2 Data-Off time OE Low to DQ Low-Z OE Access Time OE Data-Off Time Output Hold from Address READ CYCLE TIMING DIAGRAM DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ACCESS 120ns SYMBOL MIN MAX MIN t 120 ...
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... PARAMETER Write Cycle Time Address Setup Time WE Pulse Width CE and CE2 Pulse Width Data Setup Time Data Hold Time CE Data Hold Time CE2 Address Hold Time WE Data-Off Time Write Recovery Time DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ACCESS 70ns MIN MAX MIN ...
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... WRITE CYCLE TIMING—WRITE-ENABLE CONTROLLED (See Note 5) WRITE CYCLE TIMING— CE /CE2-CONTROLLED (See Note 5) DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ...
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... CE2 Before IH IL Power-Down V Fall Time PF(MAX) PF(MIN) V Fall Time PF(MIN Rise Time PF(MIN) PF(MAX) Power-Up Recover Time Expected Data-Retention Time (Oscillator On) POWER-UP/DOWN TIMING (5V DEVICE) DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC MAX UNITS NOTES s s s ...
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... PF(MIN) V Rise Time PF(MIN) PF(MAX) to RST High V PF Expected Data-Retention Time (Oscillator On) POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (T = +25C) A PARAMETER Capacitance on All Input Pins Capacitance on All Output Pins DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC SYMBOL MIN ...
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... If CE2 is used to terminate a write, the CE2 data hold time (t 6) Data-retention time is at +25C. 7) Each DS1743 has a built-in switch that disconnects the lithium source until V user. The expected t is defined for DIP modules as a cumulative time in the absence from the time power is first applied by the user ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor. DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs DOCUMENT NO. 21-0245 ...