DS1089LU-A29+ Maxim Integrated Products, DS1089LU-A29+ Datasheet - Page 8

IC ECONOSCILL 3.3V SS 8-USOP

DS1089LU-A29+

Manufacturer Part Number
DS1089LU-A29+
Description
IC ECONOSCILL 3.3V SS 8-USOP
Manufacturer
Maxim Integrated Products
Series
EconOscillator™r
Type
Clock Generatorr
Datasheet

Specifications of DS1089LU-A29+

Pll
No
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
No/No
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
Two user control signals control the output. The output
enable pin (OE) gates the output buffer and the power-
down pin (PDN) disables the master oscillator and
turns off the output for power-sensitive applications.
(Note: the power-down command must persist for at
least two output frequency cycles plus 10µs for
deglitching purposes.) On power-up, the output is dis-
abled until power is stable and the master oscillator has
generated 512 clock cycles.
Additionally, the OE input is OR’ed with the OE bit in the
ADDR register, allowing for either hardware or software
gating of the output waveform (see the Block Diagram).
Both controls feature a synchronous enable, which
ensures that there are no output glitches when the out-
put is enabled. The synchronous enable also ensures a
constant time interval (for a given frequency setting)
from an enable signal to the first output transition.
The DS1089L has the ability to reduce radiated emis-
sion peaks. The output frequency can be dithered by
±1%, ±2%, ±4%, or ±8% symmetrically around the pro-
grammed center frequency. Although the output fre-
quency changes when the dither is enabled, the duty
cycle does not change.
The dither rate (f
bits in the PRESCALER register and is enabled with the
SPRD pin. The maximum spectral attenuation occurs
when the prescaler is set to 1. The spectral attenuation
is reduced by 2.7dB for every factor of 2 that is used in
the prescaler. This happens because the prescaler’s
divider function tends to average the dither in creating
the lower frequency. However, the most stringent spec-
tral emission limits are imposed on the higher frequen-
cies where the prescaler is set to a low divider ratio.
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
can be calculated based on the master oscillator fre-
quency (see Equation 2).
where f
tor frequency, and n = divider setting (see Table 2).
3.3V Center Spread-Spectrum EconOscillator™
8
_____________________________________________________________________
MOD
= dither frequency, f
MOD
f
MOD
) is controlled by the J0 and J1
=
f
MOSC
n
MOSC
Dither Generator
Output Control
= master oscilla-
Equation 2
The dither amplitude (measured in percentage of the
master oscillator center frequency) is set using the J2
and J3 bits in the ADDR register. This circuit uses a
sense current from the master oscillator bias circuit to
adjust the amplitude of the triangle-wave signal to a
voltage level that modulates the master oscillator to a
percentage of its factory-programmed center frequen-
cy. This percentage is set in the application to be ±1%,
±2%, ±4%, or ±8% (see Table 3).
The location of bits P3, P2, P1, P0, J1, and J0 in the
PRESCALER register and bits J3 and J2 in the ADDR
register are shown in the Register Summary section.
Table 2. Dither Frequency Settings
Table 3. Dither Percentage Settings
BITS J1, J0
BITS J3, J2
00
01
10
11
00
01
10
11
Dither Percentage Settings
DITHER FREQUENCY
DITHER AMOUNT
f
f
f
MOSC
MOSC
MOSC
No dither
±1%
±2%
±4%
±8%
/ 2048
/ 4096
/ 8192

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