ICS525R-11T IDT, Integrated Device Technology Inc, ICS525R-11T Datasheet - Page 5
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ICS525R-11T
Manufacturer Part Number
ICS525R-11T
Description
IC PECL CLK USER CONFIG 28-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.ICS525-01RLFT.pdf
(10 pages)
Specifications of ICS525R-11T
Pll
Yes with Bypass
Input
Clock, Crystal
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/No
Frequency - Max
40MHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Frequency-max
40MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
525R-11T
IDT™ / ICS™ USER CONFIGURABLE CLOCK
ICS525-01/02/11/12
USER CONFIGURABLE CLOCK
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02/11/12 requries two 0.01µF
decoupling capacitors to be connected between VDD
and GND, one on each side of the chip. The capacitor
must be connected close to the device to minimize lead
inductance.
External Resistors
A 33 series termination resistor should be used on the
CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
5
Where:
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01/-11)
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01/-11)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
1. The output frequency must be in the ranges listed on
pages 3-4.
2. The phase detector frequency must be above 200
kHz.
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
The ICS525-11 has the same divider set as the -01 but
is optimized for low frequency operation.
The ICS525-12 has the same divider set as the -02 but
is optimized for low frequency operation.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
200kHz
CLK
Frequency
<
InputFrequency
---------------------------------------------- -
RDW
=
+
Input Frequency
2
ICS525-01/02/11/12 REV S 042407
2x
-------------------------------------------- -
RDW
CLOCK MULTIPLIER
VDW
+
2
+
8
OD