CY23FP12OXC-002 Cypress Semiconductor Corp, CY23FP12OXC-002 Datasheet - Page 3

• Manufacturer Part Number: CY23FP12OXC-002
• Description: IC CLK ZDB 12OUT 200MHZ 28SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY23FP12OXC-002

• Number Of Circuits: 1
• Package / Case: 28-SSOP
• Pll: Yes
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 2:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 200 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3692 - SOCKET ADAPTER FOR CY23FP12428-1918 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-07644 Rev. **
Below is a list of independent functions that can be
programmed with a volume or prototype programmer on the
“pre-programmed” silicon.
Table 1.
DC Drive Bank A
DC Drive Bank B
Output Enable for Bank B clocks
Output Enable for Bank A clocks
Inv CLKA0
Inv CLKA2
Inv CLKA4
Inv CLKB0
Inv CLKB2
Configuration
FBK
REF
/M
/N
Programs the drive strength of Bank A outputs. The user can select one out
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Programs the drive strength of Bank B outputs. The user can select one out
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled
individually if not used, to minimize electromagnetic interference (EMI) and
switching noise.
Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled
individually if not used, to minimize EMI and switching noise.
programmed, CLKA0 and CLKA1 will become complimentary pairs.
programmed, CLKA2 and CLKA3 will become complimentary pairs.
programmed, CLKA4 and CLKA5 will become complimentary pairs.
programmed, CLKB0 and CLKB1 will become complimentary pairs.
programmed, CLKB2 and CLKB3 will become complimentary pairs.
Generates an inverted clock on the CLKA0 output. When this option is
Generates an inverted clock on the CLKA2 output. When this option is
Generates an inverted clock on the CLKA4 output. When this option is
Generates an inverted clock on the CLKB0 output. When this option is
Generates an inverted clock on the CLKB2 output. When this option is
Figure 1. Basic PLL Block Diagram
PLL
/1,/2,/3,/4,
/1,/2,/3,/4,
/1,/2,/3,/4,
/1,/2,/3,/4,
/1,/2,/3,/4,
/1,/2,/3,/4,
Description
/x,/2x
/x,/2x
/x,/2x
/x,/2x
/x,/2x
/x,/2x
Function
Output
Select
Matrix
CLKA5
CLKA4
CLKA3
CLKA2
CLKB3
CLKB2
CLKB1
CLKB0
CLKA1
CLKA0
CLKB5
CLKB4
CY23FP12-002
+20 mA
+20 mA
Enable
Enable
Non-invert
Non-invert
Non-invert
Non-invert
Non-invert
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