CY2308SC-5H Cypress Semiconductor Corp, CY2308SC-5H Datasheet

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CY2308SC-5H

Manufacturer Part Number
CY2308SC-5H
Description
IC CLK ZDB 8OUT 133MHZ 16SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY2308SC-5H

Pll
Yes
Input
LVCMOS, LVTTL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
66.67MHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
133MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1362

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2308SC-5H
Manufacturer:
ICS
Quantity:
2 652
Features
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven into the
FBK pin and obtained from one of the outputs. The
input-to-output skew is less than 350 ps and output-to-output
skew is less than 200 ps.
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *H
Logic Block Diagram
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations, see
on page 3
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
3.3V operation
Industrial temperature available
REF
Available CY2308 Configurations
Extra Divider (–5H)
S2
S1
/2
Extra Divider (–3, –4)
/2
Extra Divider (–2, –3)
Select Input
198 Champion Court
Decoding
PLL
MUX
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table
on page
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 50 μA
of current draw. The PLL shuts down in two additional cases as
shown in the table
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table
CY2308–1 is the base part where the output frequencies equal
the reference if there is no counter in the feedback path. The
CY2308–1H is the high drive version of the –1 and rise and fall
times on this device are much faster.
The CY2308–2 enables the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output
frequencies depend on the output that drives the feedback pin.
The CY2308–3 enables the user to obtain 4X and 2X frequencies
on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
/2
2.
San Jose
Available CY2308 Configurations
If all output clocks are not required, Bank B is
3.3V Zero Delay Buffer
Select Input Decoding
,
CA 95134-1709
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Revised March 12, 2009
Select Input Decoding
on page 2.
on page 3. The
408-943-2600
CY2308
[+] Feedback

Related parts for CY2308SC-5H

CY2308SC-5H Summary of contents

Page 1

... Logic Block Diagram REF /2 Extra Divider (–5H Cypress Semiconductor Corporation Document Number: 38-07146 Rev. *H The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table on page 2. three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs ...

Page 2

Pinouts Table 1. Pin Definitions - 16 Pin SOIC Pin Signal [1] 1 REF [2] 2 CLKA1 [2] 3 CLKA2 GND [2] 6 CLKB1 [2] 7 CLKB2 [ [ [2] 10 CLKB3 ...

Page 3

Available CY2308 Configurations Device Feedback From CY2308–1 Bank A or Bank B CY2308–1H Bank A or Bank B CY2308–2 Bank A CY2308–2 Bank B CY2308–3 Bank A CY2308–3 Bank B CY2308–4 Bank A or Bank B CY2308–5H Bank A or ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except Ref) .............. –0. Input Voltage REF ........................................... –0 Storage Temperature .................................. –65°C to +150°C Operating Conditions for Commercial Temperature Devices Parameter V ...

Page 5

Switching Characteristics for Commercial Temperature Devices [8] Parameter Name [ Rise Time 3 (–1, –2, –3, –4) [ Rise Time 3 (–1, –2, –3, –4) [ Rise Time 3 (–1H, –5H) [ ...

Page 6

Operating Conditions for Industrial Temperature Devices Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance, below 100 MHz L Load Capacitance, from 100 MHz to 133 MHz [6] C Input Capacitance IN t Power up ...

Page 7

Switching Characteristics for Industrial Temperature Devices [8] Parameter Name [ Fall Time 4 (–1H, –5H) t Output to Output Skew on 5 same Bank (–1, –2, –3, –4) Output to Output Skew (–1H, –5H) Output Bank A to ...

Page 8

Switching Waveforms (continued) 1.4V OUTPUT OUTPUT INPUT FBK FBK, Device 1 FBK, Device 2 Document Number: 38-07146 Rev. *H Figure 5. Output-Output Skew 1. Figure 6. Input-Output Propagation Delay Figure ...

Page 9

Typical Duty Cycle [10] and I DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) Duty ...

Page 10

Typical Duty Cycle [10] and I DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) Duty ...

Page 11

... SOIC - Tape and Reel [12] CY2308SI–2 16-pin 150 mil SOIC [12] CY2308SI–2T 16-pin 150 mil SOIC - Tape and Reel [12] CY2308SC–3 16-pin 150 mil SOIC [12] CY2308SC–3T 16-pin 150 mil SOIC - Tape and Reel [12] CY2308SC–4 16-pin 150 mil SOIC [12] CY2308SC– ...

Page 12

Ordering Information (continued) Ordering Code Pb-Free CY2308SXC–1 16-pin 150 mil SOIC CY2308SXC–1T 16-pin 150 mil SOIC - Tape and Reel CY2308SXI–1 16-pin 150 mil SOIC CY2308SXI–1T 16-pin 150 mil SOIC - Tape and Reel CY2308SXC–1H 16-pin 150 mil SOIC CY2308SXC–1HT ...

Page 13

Package Drawings and Dimensions 16 Lead (150 Mil) SOIC 8 9 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Figure 8. 16-Pin TSSOP 4.40 mm Body Z16.173 1 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document ...

Page 14

... Changed IDD (PD mode) from 12.0 to 25.0 μA for Commercial and Industrial Temperature Devices Deleted Duty Cycle parameters for F < 50 MHz out Removed CY2308SI-4, CY2308SI-4T and CY2308SC-5HT. Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering Information table Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *E: Changed IDD (PD mode) from μ ...

Page 15

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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