IDTCV174CPVG8 IDT, Integrated Device Technology Inc, IDTCV174CPVG8 Datasheet - Page 5

• Manufacturer Part Number: IDTCV174CPVG8
• Description: IC FLEXPC CLK PROGR P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV174CPVG8

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV174CPVG8

SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
Symbol
V
V
T
T
T
ESD Prot
STG
AMBIENT
CASE
11-18
20-27
29-36
38-45
DDA
DD
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Bit
2-9
10
19
28
37
46
1
# of bits
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
1
8
1
8
1
8
1
8
1
8
1
Description
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Description
2000
Min
–65
0
+150
+115
Max
+70
4.6
4.6
(1)
Unit
°C
°C
°C
V
V
V
5
RESOLUTION
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit 30-37).
CPU = 100MHz
CPU = 133MHz
CPU = 166MHz
CPU = 200MHz
CPU = 266MHz
CPU = 333MHz
CPU = 400MHz
SRC = 100MHz
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
N Resolution (MHz)
COMMERCIAL TEMPERATURE RANGE
0.500000
0.666667
0.666667
1.000000
1.333333
1.333333
2.000000
0.500000
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes)
:
Description
0.5%
0.5%
0.4%
0.5%
0.5%
0.4%
0.5%
0.5%
%
N =
200
200
250
200
200
250
200
200