IDTCV115-2PV IDT, Integrated Device Technology Inc, IDTCV115-2PV Datasheet - Page 4

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IDTCV115-2PV

Manufacturer Part Number
IDTCV115-2PV
Description
IC FLEXPC CLK PROGR P4 56-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
FlexPC™r
Type
PC Clockr
Datasheet

Specifications of IDTCV115-2PV

Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
CV115-2PV

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDTCV115-2PV
Manufacturer:
IDT
Quantity:
6 227
Part Number:
IDTCV115-2PV8
Manufacturer:
IDT
Quantity:
20 000
PIN DESCRIPTION (CONT.)
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
Pin Number
11-18
20-27
29-36
38-45
Bit
2-9
10
19
28
37
46
1
47
48
49
50
51
52
53
54
55
56
# of bits
1
8
1
8
1
8
1
8
1
8
1
FS_A(REF1/PCI5)
V
FS_C/REF0
XTAL_OUT
Master
Master
Master
Master
Master
Master
Master
Master
DD
From
Slave
Slave
Slave
Slave
Slave
V
Slave
XTAL_IN
V
DD
SS
_Suspend
Name
PCI0
PCI1
SCL
_REF
_REF
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N, (0 is not valid
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
POWER
Type
PWR
GND
OUT
OUT
OUT
I/O
I/O
I N
IN
Description
SMBus CLK
3.3V
Xtal output
Xtal input
GND
CPU frequency selection input at V
Keep supply 3.3V in the power down
CPU frequency selection input at V
SMBus selectable. Tristate at power on.
PCI clock
PCI clock
4
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
TT
TT
1
8
1
8
1
1
8
1
8
1
8
1
8
_P
_P
WRGD
WRGD
assertion. 14.318 or PCI reference clock output afterward,
assertion. 14.318 reference clock output afterward.
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Description
COMMERCIAL TEMPERATURE RANGE
Start
D2H
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3H
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes), Byte 8
:
Description

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