LFXP6C-5F256C LATTICE SEMICONDUCTOR, LFXP6C-5F256C Datasheet - Page 9
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LFXP6C-5F256C
Manufacturer Part Number
LFXP6C-5F256C
Description
FPGA LatticeXP Family 6000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP6C-5F256C
Package
256FBGA
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
400 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
188
Ram Bits
73728
Re-programmability Support
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-5F256C
Manufacturer:
LATTICE
Quantity:
44
Company:
Part Number:
LFXP6C-5F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFXP6C-5F256C-4I
Manufacturer:
MAXIM
Quantity:
1 034
Lattice Semiconductor
Table 2-4. PFU Modes of Operation
Routing
There are many resources provided in the LatticeXP devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. The
x2 and x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. Lat-
ticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four
dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources.
1. These modes are not available in PFF blocks
MUX 16x1 x 1
MUX 2x1 x 8
MUX 4x1 x 4
MUX 8x1 x 2
LUT 6x 2 or
LUT 4x8 or
LUT 5x4 or
LUT 7x1 or
Logic
2-bit Counter x 4
2-bit Comp x 4
2-bit Add x 4
2-bit Sub x 4
Ripple
2-6
DPR16x2 x 2
DPR16x4 x 1
SPR16x2 x 4
SPR16x4 x 2
SPR16x8 x 1
RAM
1
LatticeXP Family Data Sheet
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
ROM
Architecture