LFXP15C-3FN388C LATTICE SEMICONDUCTOR, LFXP15C-3FN388C Datasheet - Page 14
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LFXP15C-3FN388C
Manufacturer Part Number
LFXP15C-3FN388C
Description
FPGA LatticeXP Family 15000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP15C-3FN388C
Package
388FBGA
Family Name
LatticeXP
Device Logic Units
15000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
268
Ram Bits
331776
Re-programmability Support
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP15C-3FN388C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates
the DCS Block Macro.
Figure 2-12. DCS Block Primitive
CLK0
CLK1
DCS
DCSOUT
SEL
Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-13. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of
a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
2-11
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