LFEC3E-3FN256C LATTICE SEMICONDUCTOR, LFEC3E-3FN256C Datasheet - Page 6
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LFEC3E-3FN256C
Manufacturer Part Number
LFEC3E-3FN256C
Description
FPGA LatticeEC Family 3100 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-3FN256C
Package
256FBGA
Family Name
LatticeEC
Device Logic Units
3100
Maximum Internal Frequency
340 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
160
Ram Bits
56320
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
PFU and PFF Blocks
The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Latch
FF/
LUT4 &
CARRY
D
Slice 0
Latch
FF/
LUT4 &
CARRY
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
LUT4 &
CARRY
D
Routing
Routing
From
2-3
To
Latch
FF/
LUT4 &
CARRY
D
Slice 2
Latch
FF/
LUT4 &
CARRY
LatticeECP/EC Family Data Sheet
D
Latch
FF/
LUT4 &
CARRY
D
Slice 3
Latch
FF/
LUT4 &
CARRY
D
Architecture
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