LFEC3E-3FN256C LATTICE SEMICONDUCTOR, LFEC3E-3FN256C Datasheet - Page 27
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LFEC3E-3FN256C
Manufacturer Part Number
LFEC3E-3FN256C
Description
FPGA LatticeEC Family 3100 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-3FN256C
Package
256FBGA
Family Name
LatticeEC
Device Logic Units
3100
Maximum Internal Frequency
340 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
160
Ram Bits
56320
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-27. Input Register DDR Waveforms
Figure 2-28. INDDRXB Primitive
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-29 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
(In DDR Mode)
Delayed
DQS
DQS
D0
D2
DI
DDRCLKPOL
A
ECLK
SCLK
LSR
CE
D
B
2-24
IDDRXB
C
B
A
QA
QB
LatticeECP/EC Family Data Sheet
D
E
D
C
F
Architecture
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