ISPLSI 1016E-80LJN LATTICE SEMICONDUCTOR, ISPLSI 1016E-80LJN Datasheet - Page 7
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ISPLSI 1016E-80LJN
Manufacturer Part Number
ISPLSI 1016E-80LJN
Description
CPLD ispLSI® 1000E Family 2K Gates 64 Macro Cells 84MHz EECMOS Technology 5V 44-Pin PLCC
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.ISPLSI_1016E-100LJ.pdf
(13 pages)
Specifications of ISPLSI 1016E-80LJN
Package
44PLCC
Family Name
ispLSI® 1000E
Device System Gates
2000
Number Of Macro Cells
64
Maximum Propagation Delay Time
18.5 ns
Number Of User I/os
32
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
84 MHz
Operating Temperature
0 to 70 °C
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
PARAMETER
Internal Timing Parameters
Outputs
t
t
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
sl
oen
odis
goe
gy0
gy1/2
gcp
ioy1/2
iocp
gr
49 Output Buffer Delay
50 Output Slew Limited Delay Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global Output Enable
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
59 Global Reset to GLB and I/O Registers
#
2
1
DESCRIPTION
7
Specifications ispLSI 1016E
MIN.
1.3
2.3
0.8
0.0
0.8
–
–
–
–
–
–
-125
MAX.
10.0
3.2
1.4
4.3
4.3
2.7
1.3
2.7
1.8
0.3
1.8
MIN.
1.4
2.4
0.8
0.0
0.8
–
–
–
–
–
–
-100
MAX.
10.0
4.5
1.7
5.3
5.3
3.7
1.4
2.9
1.8
0.4
1.8
MIN. MAX.
2.1
3.6
1.2
0.0
1.2
–
–
–
–
–
–
Table 2-0037-16/125,100,80
-80
10.0
3.0
6.4
6.4
4.1
2.1
4.4
2.7
0.6
2.7
5.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns