MT47H32M8BP-5E IT:B TR Micron Technology Inc, MT47H32M8BP-5E IT:B TR Datasheet - Page 73
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MT47H32M8BP-5E IT:B TR
Manufacturer Part Number
MT47H32M8BP-5E IT:B TR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M8BP-5E_ITB_TR.pdf
(128 pages)
Specifications of MT47H32M8BP-5E IT:B TR
Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
600ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
125mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
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Write Recovery
Power-Down Mode
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 71).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 63 (page 106).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing
nanoseconds) by
integer; WR (cycles) =
known operation or incompatibility with future versions may result.
Active power-down (PD) mode is defined by bit M12, as shown in Figure 34. PD mode
enables the user to determine the active power-down mode, which determines perform-
ance versus power savings. PD mode bit M12 does not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I
power mode is defined in the DDR2 I
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
t
CK (in nanoseconds) and rounding up a noninteger value to the next
t
WR (ns)/
73
t
CK (ns). Reserved states should not be used as an un-
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Specifications and Conditions table.
256Mb: x4, x8, x16 DDR2 SDRAM
DD3P
Mode Register (MR)
©2003 Micron Technology, Inc. All rights reserved.
normal and I
t
WR (in
DD3P
low-
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