SC16C852VIET,551 NXP Semiconductors, SC16C852VIET,551 Datasheet - Page 34
SC16C852VIET,551
Manufacturer Part Number
SC16C852VIET,551
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C852VIET551.pdf
(55 pages)
Specifications of SC16C852VIET,551
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Number Of Channels
2
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SC16C852V
Product data sheet
7.15 Transmit Interrupt Level register (TXINTLVL)
7.16 Receive Interrupt Level register (RXINTLVL)
Table 26.
[1]
This 8-bit register is used store the transmit FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1.
Table 27.
[1]
This 8-bit register is used store the receive FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 28
Table 28.
[1]
Cont-3
1
X
X
X
1
0
1
Bit
7:0
Bit
7:0
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
Table 27
TXINTLVL[7:0]
RXINTLVL[7:0]
Symbol
Symbol
shows trigger level register bit settings.
Cont-2
1
X
X
X
0
1
1
Software flow control functions
TXINTLVL register bits description
RXINTLVL register bits description
shows trigger level register bit settings.
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Cont-1
X
0
1
0
1
1
1
Rev. 5 — 21 January 2011
This register stores the programmable transmit interrupt trigger levels for
This register stores the programmable receive interrupt trigger levels for
Description
128-byte FIFO mode.
Description
128-byte FIFO mode.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Cont-0
X
0
0
1
1
1
1
Section 7.3 “FIFO Control Register
Section 7.3 “FIFO Control Register
TX, RX software flow controls
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
[1]
[1]
[1]
…continued
(FCR)”.
(FCR)”.
SC16C852V
© NXP B.V. 2011. All rights reserved.
34 of 55