MCIMX31DVMN5DR2 Freescale, MCIMX31DVMN5DR2 Datasheet - Page 48
MCIMX31DVMN5DR2
Manufacturer Part Number
MCIMX31DVMN5DR2
Description
Manufacturer
Freescale
Datasheet
1.MCIMX31DVMN5DR2.pdf
(118 pages)
Specifications of MCIMX31DVMN5DR2
Operating Temperature (min)
-20C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Electrical Characteristics
48
1
SD11 and SD12 are determined by SDRAM controller register settings.
SD1
SD2
SD13
SD14
ID
ADDR
ID
RAS
CAS
SDCLK
SDCLK
WE
CS
SD6
SDRAM clock high-level width
SDRAM clock low-level width
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Data setup time
Data hold time
BA
Table 34. SDR SDRAM Write Timing Parameters (continued)
SD7
Parameter
Table 35. SDRAM Refresh Timing Parameters
Table 34
Figure 35. SDRAM Refresh Timing Diagram
SD11
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Parameter
indicates SDRAM requirements. All output signals
NOTE
SD10
Symbol
tCH
tCL
SD1
SD3
Symbol
tDH
tDS
SD2
Min
SD10
3.4
3.4
Min
2.0
1.3
ROW/BA
Freescale Semiconductor
Max
4.1
4.1
Max
—
—
Unit
Unit
ns
ns
ns
ns
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