LM629M-8/HALF National Semiconductor, LM629M-8/HALF Datasheet - Page 17
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LM629M-8/HALF
Manufacturer Part Number
LM629M-8/HALF
Description
Manufacturer
National Semiconductor
Datasheet
1.LM629M-8HALF.pdf
(26 pages)
Specifications of LM629M-8/HALF
Operating Current
110mA
Operating Temperature Classification
Industrial
Package Type
SOIC W
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Compliant
Data Reporting Commands
LPEI or LPES has been exceeded. The flag is functional
independent of the host interrupt mask status. Bit 5 is
cleared via command RSTI.
Bit 4, the wraparound interrupt flag, is set to logic one when
a numerical “wraparound” has occurred. To “wraparound”
means to exceed the position address space of the LM628,
which could occur during velocity mode operation. If a wrap-
around has occurred, then position information will be in
error and this interrupt helps the user to ensure position data
integrity. The flag is functional independent of the host inter-
rupt mask status. Bit 4 is cleared via command RSTI.
Bit 3, the index-pulse acquired interrupt flag, is set to logic
one when an index pulse has occurred (if command SIP had
been executed) and indicates that the index position register
has been updated. The flag is functional independent of the
host interrupt mask status. Bit 3 is cleared by command
RSTI.
Bit 2, the trajectory complete interrupt flag, is set to logic one
when the trajectory programmed by the LTRJ command and
initiated by the STT command has been completed. Be-
cause of overshoot or a limiting condition (such as com-
manding the velocity to be higher than the motor can
achieve), the motor may not yet be at the final commanded
position. This bit is the logical OR of bits 7 and 10 of the
Signals Register, see command RDSIGS below. The flag
functions independently of the host interrupt mask status. Bit
2 is cleared via command RSTI.
Bit 1, the command-error interrupt flag, is set to logic one
when the user attempts to read data when a write was
appropriate (or vice versa). The flag is functional indepen-
dent of the host interrupt mask status. Bit 1 is cleared via
command RSTI.
Bit 0, the busy flag, is frequently tested by the user (via the
host computer program) to determine the busy/ready status
prior to writing and reading any data. Such writes and reads
may be executed only when bit 0 is logic zero (not busy). Any
command or data writes when the busy bit is high will be
ignored. Any data reads when the busy bit is high will read
the current contents of the I/O port buffers, not the data
expected by the host. Such reads or writes (with the busy bit
high) will not generate a command-error interrupt.
RDSIGS COMMAND: READ SIGNALS REGISTER
The LM628 internal “signals” register may be read using this
command. The first byte read is the more significant. The
less significant byte of this register (with the exception of bit
0) duplicates the status byte. See Table 8.
(Continued)
Bit Position
Command Code:
Bytes Read:
Data Range:
Executable During Motion: Yes
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
TABLE 8. Signals Register Bit Allocation
Host Interrupt
Acceleration Loaded (But Not Updated)
UDF Executed (But Filter Not yet Updated)
Forward Direction
Velocity Mode
0C Hex
Two
See Text
Function
17
Bit 15, the host interrupt flag, is set to logic one when the
host interrupt output (Pin 17) is logic one. Pin 17 is set to
logic one when any of the six host interrupt conditions occur
(if the corresponding interrupt has not been masked). Bit 15
(and Pin 17) are cleared via command RSTI.
Bit 14, the acceleration-loaded flag, is set to logic one when
acceleration data is written to the LM628. Bit 14 is cleared by
the STT command.
Bit 13, the UDF-executed flag, is set to logic one when the
UDF command is executed. Because bit 13 is cleared at the
end of the sampling interval in which it has been set, this
signal is very short-lived and probably not very profitable for
monitoring.
Bit 12, the forward direction flag, is meaningful only when the
LM628 is in velocity mode. The bit is set to logic one to
indicate that the desired direction of motion is “forward”; zero
indicates “reverse” direction. Bit 12 is set and cleared via
command LTRJ. The actual setting and clearing of bit 12
does not occur until command STT is executed.
Bit 11, the velocity mode flag, is set to logic one to indicate
that the user has selected (via command LTRJ) velocity
mode. Bit 11 is cleared when position mode is selected (via
command LTRJ). The actual setting and clearing of bit 11
does not occur until command STT is executed.
Bit 10, the on-target flag, is set to logic one when the
trajectory generator has completed its functions for the last-
issued STT command. Bit 10 is cleared by the next STT
command.
Bit 9, the turn-off on-error flag, is set to logic one when
command LPES is executed. Bit 9 is cleared by command
LPEI.
Bit 8, the 8-bit output flag, is set to logic one when the LM628
is reset, or when command PORT8 is executed. Bit 8 is
cleared by command PORT12.
Bits 0 through 7 replicate the status byte (see ), with the
exception of bit 0. Bit 0, the acquire next index flag, is set to
logic one when command SIP is executed; it then remains
set until the next index pulse occurs.
RDIP COMMAND: READ INDEX POSITION
This command reads the position recorded in the index
register. Reading the index register can be part of a system
error checking scheme. Whenever the SIP command is ex-
ecuted, the new index position minus the old index position,
Bit Position
Command Code:
Bytes Read:
Data Range:
Executable During Motion: Yes
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
On Target
Turn Off upon Excessive Position Error
Eight-Bit Output Mode
Motor Off
Breakpoint Reached [Interrupt]
Excessive Position Error [Interrupt]
Wraparound Occurred [Interrupt]
Index Pulse Acquired [Interrupt]
Trajectory Complete [Interrupt]
Command Error [Interrupt]
Acquire Next Index (SIP Executed)
09 Hex
Four
C0000000 to 3FFFFFFF Hex
Function
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