MC34713EP Freescale, MC34713EP Datasheet - Page 18

• Manufacturer Part Number: MC34713EP
• Manufacturer: Freescale

Specifications of MC34713EP

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 24
• Mounting: Surface Mount
• Package Type: QFN
• Case Length: 4mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Compliant

achieve a faster response and a proper phase margin,
BOOTSTRAP CAPACITOR
voltage for the high side MOSFET. This N-Channel MOSFET
needs a voltage difference between its gate and source to be
able to turn on. The high side MOSFET source is the SW
node, so it is not ground and it is floating and moving in
voltage, so we cannot just apply a voltage directly to the gate
of the high side that is referenced to ground, we need a
voltage referenced to the SW node. That is why the bootstrap
capacitor is needed for. This capacitor charges during the
high side off time, since the low side will be on during that
time, so the SW node and the bottom of the bootstrap
capacitor will be connected to ground and the top of the
capacitor will be connected to a voltage source, so the
capacitor will charge up to that voltage source (say 5.0 V).
Now when the low side MOSFET switches off and the high
side MOSFET switches on, the SW nodes rises up to Vin,
and the voltage on the boot pin will be Vcap + Vin. So the gate
of the high side will have Vcap across it and it will be able to
18
34713
TYPICAL APPLICATIONS
Equating the Pole 2 to 5 times the Crossover Frequency to
The bootstrap capacitor is needed to supply the gate
5
•
⇒
F
CROSS
⇒
=
F P2
=
---------------------------------------- -
2π R
•
F
1
-------------------- -
C
C
F
F
+
C
C
X
X
stay enhanced. A 0.1 μF capacitor is a good value for this
bootstrap element.
LAYOUT GUIDELINES
consideration. First, there are high di/dt signals present, and
the traces carrying these signals need to be kept as short and
as wide as possible to minimize the trace inductance, and
therefore reduce the voltage spikes they can create. To do
this, an understanding of the major current carrying loops is
important. See
components, should be placed in such a way as to minimize
the loop size to prevent coupling to other parts of the circuit.
Also, the current carrying power traces and their associated
return traces should run adjacent to one another, to minimize
the amount of noise coupling. If sensitive traces must cross
the current carrying traces, they should be made
perpendicular to one another to reduce field interaction.
sensitive nodes need consideration. The critical small signal
components are the ones associated with the feedback
circuit. The high impedance input of the error amp is
especially sensitive to noise, and the feedback and
compensation components should be placed as far from the
switch node, and as close to the input of the error amplifier as
possible. Other critical small signal components include the
bypass capacitors for VIN, VREFIN, and VDDI. Locate the
bypass capacitors as close to the pin as possible.
recommended. Dedicate one layer, usually the layer under
the top layer, as a ground plane. Make all critical component
ground connections with vias to this layer. Make sure that the
power ground, PGND, is connected directly to the ground
plane and not routed through the thermal pad or analog
ground. Dedicate another layer as a power plane and split
this plane into local areas for common voltage nets.
dedicated trace to the input supply. This will help prevent
noise from the Buck Regulator's power input (PVIN) from
injecting switching noise into the IC’s analog circuitry.
ground plane and other layers of the printed circuit board,
thermal vias need to be used in the thermal pad design. It is
recommended that 5 to 9 vias be spaced evenly and have a
finished diameter of 0.3 mm.
The layout of any switching regulator requires careful
Second, small signal components which connect to
The use of a multi-layer printed circuit board is
The IC input supply (VIN) should be connected with a
In order to effectively transfer heat from the top layer to the
Figure
10. These loops, and their associated
Analog Integrated Circuit Device Data
Freescale Semiconductor