CY7C433-20AC Cypress Semiconductor Corp, CY7C433-20AC Datasheet - Page 12
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CY7C433-20AC
Manufacturer Part Number
CY7C433-20AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C433-20AC.pdf
(16 pages)
Specifications of CY7C433-20AC
Configuration
Dual
Density
36Kb
Access Time (max)
20ns
Word Size
9b
Organization
4Kx9
Sync/async
Asynchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C433-20AC
Manufacturer:
CYPR
Quantity:
5 678
Use of the Empty and Full Flags
To achieve maximum frequency, the flags must be valid at the
beginning of the next cycle. However, because they can be
updated by either edge of the read or write signal, they must be
valid by one-half of a cycle. Cypress FIFOs meet this
requirement; some competitors’ FIFOs do not.
The reason for why the flags should be valid by the next cycle is
complex. The “effective pulse width violation” phenomenon can
occur at the full and empty boundary conditions, if the flags are
not properly used. The empty flag must be used to prevent
reading from an empty FIFO and the full flag must be used to
prevent writing into a full FIFO.
Document #: 38-06001 Rev. *D
FULL
W
D
MR
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Figure 13. Depth Expansion
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CY7C419
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For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored
by the FIFO, and nothing happens. Next, a single word is written
into the FIFO, with a signal that is asynchronous to the read
signal. The (internal) state machine in the FIFO goes from empty
to empty+1. However, it does this asynchronously with respect
to the read signal, so that the effective pulse width of the read
signal cannot be determined, because the state machine does
not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by
trying to write into a full FIFO, and asynchronously performing a
read. The empty and full flags are used to avoid these effective
pulse width violations, but to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
*
* FIRST DEVICE
EF
EF
EF
FL
FL
FL
CY7C419/21/25/29/33
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Page 12 of 16
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