MT46V64M8P-6TLAT:F Micron Technology Inc, MT46V64M8P-6TLAT:F Datasheet - Page 77
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MT46V64M8P-6TLAT:F
Manufacturer Part Number
MT46V64M8P-6TLAT:F
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V64M8P-6TLATF.pdf
(91 pages)
Specifications of MT46V64M8P-6TLAT:F
Lead Free Status / RoHS Status
Compliant
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Figure 42:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-READ – Uninterrupting
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b; DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE
6. A10 is LOW with the WRITE command (auto precharge is disabled).
t
commands may be to different devices, in which case
command could be applied earlier.
DI
b
WTR is referenced from the first positive CK edge after the last data-in pair.
NOP
DI
T1
b
DI
b
T1n
NOP
T2
T2n
77
NOP
T3
t
WTR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Bank a,
READ
T4
Col n
512Mb: x4, x8, x16 DDR SDRAM
Transitioning Data
t
WTR is not required, and the READ
CL = 2
CL = 2
CL = 2
T5
NOP
©2000 Micron Technology, Inc. All rights reserved.
T6
NOP
Operations
Don’t Care
DO
DO
DO
n
n
n
T6n
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