MT48LC16M4A2TG-7EL Micron Technology Inc, MT48LC16M4A2TG-7EL Datasheet - Page 14
MT48LC16M4A2TG-7EL
Manufacturer Part Number
MT48LC16M4A2TG-7EL
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC16M4A2TG-7EL.pdf
(72 pages)
Specifications of MT48LC16M4A2TG-7EL
Lead Free Status / RoHS Status
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Burst Length
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
READ and WRITE accesses to the SDRAM are burst oriented, with the burst length (BL)
being programmable, as shown in Figure 6 on page 15. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE
command. BL = 1, 2, 4, or 8 locations are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available for the sequential mode. The full-
page burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states cannot be used because unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A9 (x4), A1–A8 (x8) or A1–A7 (x16) when BL = 2; by A2–A9 (x4),
A2–A8 (x8) or A2–A7 (x16) when BL = 4; and by A3–A9 (x4), A3–A8 (x8) or A3–A7 (x16)
when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap within the page if the boundary
is reached.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: x4, x8, x16 SDRAM
Functional Description
©2000 Micron Technology, Inc. All rights reserved.
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