AM41DL1624DT85I Spansion Inc., AM41DL1624DT85I Datasheet - Page 57
AM41DL1624DT85I
Manufacturer Part Number
AM41DL1624DT85I
Description
Manufacturer
Spansion Inc.
Datasheet
1.AM41DL1624DT85I.pdf
(63 pages)
Specifications of AM41DL1624DT85I
Operating Supply Voltage (max)
3.3V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
3. t
4. t
5. A write occurs during the overlap (t
56
Parameter
Symbol
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
t
t
t
t
t
t
t
t
t
WHZ
t
t
WC
AW
BW
WP
WR
DW
OW
Cw
DH
is measured from the address valid to the beginning of write.
AS
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
Address
CS1#s
CS2s
UB#s, LB#s
WE#
Data In
Data Out
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Figure 30. SRAM Write Cycle—WE# Control
WP
Data Undefined
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
(See Note 4)
P R E L I M I N A R Y
t
AS
Am41DL16x4D
t
BW
(See Note 2)
(See Note 2)
WR
t
AW
applied in case a write ends as CE1#s or WE# going high.
(See Note 5)
t
WC
t
t
t
CW
BW
CW
t
WP
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
t
DW
Data Valid
WP
is measured from the beginning of write
t
WR
t
DH
70
70
60
60
60
50
20
30
Speed Options
t
(See Note 3)
OW
0
0
0
0
5
High-Z
85
85
70
70
70
60
25
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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