IDT92HD71B8X5PRGXB3X8 IDT, Integrated Device Technology Inc, IDT92HD71B8X5PRGXB3X8 Datasheet - Page 18
IDT92HD71B8X5PRGXB3X8
Manufacturer Part Number
IDT92HD71B8X5PRGXB3X8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT92HD71B8X5PRGXB3X8.pdf
(216 pages)
Specifications of IDT92HD71B8X5PRGXB3X8
Package Type
TQFP
Lead Free Status / RoHS Status
Compliant
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
D0-D3
0
92HD71B8
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
Digital Mics
AFG Power
State
1.4.13. Digital Microphone Support
N/A
Data Sample
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Asserted (Low)
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the
DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry
individual channels of digital Mic data to the ADC. In the event that a single microphone is used, the
data is ported to both ADC channels.
The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-
chronous to the 24Mhz internal clock. The default frequency is 2.352Mhz.
92HD71B8 supports the following digital microphone configurations:
RESET#
N/A
ADC Conn.
Table 8. Valid Digital Mic Configurations
GPIO Enable
Disabled
Disabled
Disabled
Enabled
No Digital Microphones
-
Table 7. EAPD Behavior
Output Enable
18
Disabled
Disabled
Enabled
-
-
EAPD Power
D2-D3
D0-D1
State
-
-
-
Notes
92HD71B8
output (internal pull-down enabled)
Active - Pin drives the value of the
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Active - Pin Drives SPDIFOut0/1
retained until the rising edge of
otherwise the previous state is
configuration (internal pull-up
EAPD bit (internal pull-down
immediately after power on,
Active - Pin reflects GPIO0
Pin Behavior
RESET#
enabled)
enabled)
PC AUDIO
V 1.0, 01/08
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