ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 98

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7342/ADV7343
Table 100. 8-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 101. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 102. 8-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 103. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 104. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Setting
0x02
0x1C
0x20
0x18
0x01
Setting
0x02
0x1C
0x20
0x10
0x1C
0x01
Setting
0x02
0x1C
0x20
0x10
0x18
0x01
Setting
0x02
0x1C
0x10
0x1C
0x01
Setting
0x02
0x1C
0x10
0x18
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Rev. A | Page 98 of 104
Table 105. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 106. 16-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 107. 24-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 108. 24-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 109. 24-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
0x02
0x1C
0x10
0x10
0x1C
0x01
0x02
0x1C
0x10
0x10
0x18
0x01
0x02
0x1C
0x10
0x1C
0x01
0x28
0x02
0x1C
0x10
0x18
0x01
0x28
0x02
0x1C
0x10
0x10
0x1C
0x01
0x28
Setting
Setting
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.