SAF7118EH/V1/G-T NXP Semiconductors, SAF7118EH/V1/G-T Datasheet - Page 164
SAF7118EH/V1/G-T
Manufacturer Part Number
SAF7118EH/V1/G-T
Description
Video ICs 9BIT VIDEO DECODER
Manufacturer
NXP Semiconductors
Datasheet
1.SAF7118EHV1G-T.pdf
(175 pages)
Specifications of SAF7118EH/V1/G-T
Screening Level
Industrial
Package Type
HBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
Other names
SAF7118EH/V1/G,518
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19. Appendix
SAF7118_4
Product data sheet
19.1 Issue 1: Bit ICKS3 = 1 (I
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description” .
80h) drives image port output clock ICLK to 3-state
Background (how it should work):
The control signal ICKS[3:0] is intended to be used to switch the image port clock I/O into
different operating modes.
ICKS[1:0] = 11b should 3-state the ICLK output (for using the pin as external back-end
clock input). ICKS3 influences the generation of the data qualifier; see
Anomaly description:
ICKS3 is erroneously connected to the 3-state control block instead of ICKS[1:0].
Impact:
Workaround:
1. ICKS[1:0] = 11b does not switch ICLK to 3-state
2. If ICKS3 needs to be used according to the extended function on IDQ (see
1. If external ICLK is required, ICKS3 has to be set to logic 1 in addition to
2. Use pin LLC as reference clock instead of ICLK, if ICKS3 needs to be programmed to
Fig 98. Temperature profiles for large and small components
the ICLK output will be 3-stated and cannot be used anymore
ICKS[1:0] = 11b
logic 1
temperature
MSL: Moisture Sensitivity Level
Rev. 04 — 4 July 2008
= minimum soldering temperature
maximum peak temperature
minimum peak temperature
2
= MSL limit, damage level
Multistandard video decoder with adaptive comb filter
C-bus control signal, bit D3 of subaddress
temperature
peak
SAF7118
Table
© NXP B.V. 2008. All rights reserved.
001aac844
93.
time
Table
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