PIC24F16KA302-E/SP Microchip Technology, PIC24F16KA302-E/SP Datasheet - Page 77
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PIC24F16KA302-E/SP
Manufacturer Part Number
PIC24F16KA302-E/SP
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 28 SPDIP .300in
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.PIC24F16KA301T-ISO.pdf
(320 pages)
Specifications of PIC24F16KA302-E/SP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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7.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer (OST) has not
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known.
7.2.2
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC Oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
7.3
Most of the Special Function Registers (SFRs)
associated with the PIC24F CPU and peripherals are
reset to a particular value at a device Reset. The SFRs
are grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in the Flash Configuration
Word (FOSCSEL); see
NVMCON registers are only affected by a POR.
7.4
Deep Sleep BOR is a very low-power BOR circuitry,
used when the device is in Deep Sleep mode. Due to
low current consumption, accuracy may vary.
The DSBOR trip point is around 2.0V. DSBOR is
enabled by configuring DSLPBOR (FDS<6>) = 1.
DSLPBOR will re-arm the POR to ensure the device will
reset if V
2011 Microchip Technology Inc.
expired (if a crystal oscillator is used).
DD
Special Function Register Reset
States
Deep Sleep BOR (DSBOR)
POR AND LONG OSCILLATOR
START-UP TIMES
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
drops below the POR threshold.
Table
7-2. The RCFGCAL and
PIC24FV32KA304 FAMILY
7.5
The PIC24FV32KA304 family devices implement a
BOR circuit, which provides the user several
configuration and power-saving options. The BOR is
controlled by the BORV<1:0> and BOREN<1:0>
Configuration bits (FPOR<6:5,1:0>). There are a total
of four BOR configurations, which are provided in
Table
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of V
reset the device. The chip will remain in BOR until V
rises above the threshold.
If the Power-up Timer is enabled, it will be invoked after
V
in Reset for an additional time delay, T
drops below the threshold while the power-up timer is
running. The chip goes back into a BOR and the
Power-up Timer will be initialized. Once V
the threshold, the Power-up Timer will execute the
additional time delay.
BOR and the Power-up Timer (PWRT) are indepen-
dently configured. Enabling the BOR Reset does not
automatically enable the PWRT.
7.5.1
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<13>). Setting SBOREN
enables the BOR to function as previously described.
Clearing the SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise, it is
read as ‘0’.
Placing BOR under software control gives the user the
additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor the incremental current that the BOR
consumes. While the BOR current is typically very
small, it may have some impact in low-power
applications.
DD
Note:
rises above the threshold; then, it will keep the chip
7-3.
Brown-out Reset (BOR)
SOFTWARE ENABLED BOR
Even when the BOR is under software
control, the BOR Reset voltage level is still
set by the BORV<1:0> Configuration bits.
It can not be changed in software.
DD
below the set threshold point will
DS39995B-page 77
DD
PWRT
rises above
, if V
DD
DD
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