PIC24F16KA302-E/SP Microchip Technology, PIC24F16KA302-E/SP Datasheet - Page 180
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC24F16KA302-E/SP
Manufacturer Part Number
PIC24F16KA302-E/SP
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 28 SPDIP .300in
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.PIC24F16KA301T-ISO.pdf
(320 pages)
Specifications of PIC24F16KA302-E/SP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC24FV32KA304 FAMILY
REGISTER 17-3:
REGISTER 17-4:
DS39995B-page 180
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5
bit 4
bit 3-0
AMSK7
R/W-0
U-0
U-0
U-0
—
—
—
Unimplemented: Read as ‘0’
SMBUSDEL2: SMBus SDAx Input Delay Select bit
1 = The I2C2 module is configured for a longer SMBus input delay (nominal 300 ns delay)
0 = The I2C2 module is configured for a legacy input delay (nominal 150 ns delay)
SMBUSDEL1: SMBus SDAx Input Delay Select bit
1 = The I2C1 module is configured for a longer SMBus input delay (nominal 300 ns delay)
0 = The I2C1 module is configured for a legacy input delay (nominal 150 ns delay)
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match not is required in this position
0 = Disable masking for bit x; bit match is required in this position
U-0
U-0
—
—
AMSK6
R/W-0
U-0
—
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
SMBUSDEL2 SMBUSDEL1
W = Writable bit
‘1’ = Bit is set
R/W-0
W = Writable bit
‘1’ = Bit is set
U-0
—
AMSK5
R/W-0
U-0
—
R/W-0
U-0
—
AMSK4
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
AMSK3
R/W-0
U-0
—
U-0
U-0
—
—
AMSK2
R/W-0
U-0
—
2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
AMSK9
AMSK1
R/W-0
R/W-0
U-0
U-0
—
—
AMSK8
AMSK0
R/W-0
R/W-0
U-0
U-0
—
—
bit 8
bit 0
bit 8
bit 0
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