PIC18F26J13-I/SP Microchip Technology, PIC18F26J13-I/SP Datasheet - Page 70
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F26J13-I/SP
Manufacturer Part Number
PIC18F26J13-I/SP
Description
28-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SPDIP .300
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F26J13-ISS.pdf
(496 pages)
2.PIC18F26J13-ISS.pdf
(558 pages)
3.PIC18F26J13-ISS.pdf
(12 pages)
Specifications of PIC18F26J13-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PIC18(L)F2X/4XK22
FIGURE 5-1:
5.1.1
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
DS41412D-page 70
PIC18(L)F23K22
PIC18(L)F43K22
Program Memory
PROGRAM COUNTER
CALL,RCALL,RETURN
RETFIE,RETLW
Read ‘0’
On-Chip
PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES
1FFFh
2000h
Section 5.1.4.1 “Computed
PIC18(L)F24K22
PIC18(L)F44K22
Program Memory
Read ‘0’
On-Chip
High Priority Interrupt Vector
Low Priority Interrupt Vector
Stack Level 31
3FFFh
4000h
Stack Level 1
Reset Vector
PC<20:0>
Preliminary
PIC18(L)F25K22
PIC18(L)F45K22
Program Memory
On-Chip
Read ‘0’
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack (TOS) Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
7FFFh
8000h
PIC18(L)F26K22
PIC18(L)F46K22
Program Memory
21
RETURN ADDRESS STACK
On-Chip
Read ‘0’
10000h
FFFFh
2010 Microchip Technology Inc.
0000h
0008h
0018h
1FFFFFh
200000h
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