PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 6
PRLXT9785BC.D0 S L7WP
Manufacturer Part Number
PRLXT9785BC.D0 S L7WP
Description
Manufacturer
Intel
Datasheet
1.PRLXT9785BC.D0_S_L7WP.pdf
(234 pages)
Specifications of PRLXT9785BC.D0 S L7WP
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Contents
6.0
7.0
8.0
9.0
Figures
1
2
3
4
5
6
7
8
9
10 Management Interface Write Frame Structure ......................................................................... 121
11 Port Address Scheme............................................................................................................... 122
12 Interrupt Logic........................................................................................................................... 123
13 Initialization Sequence.............................................................................................................. 126
14 Auto-Negotiation Operation ...................................................................................................... 130
15 Typical SMII Interface ............................................................................................................... 132
16 Typical SMII Quad Sectionalization .......................................................................................... 133
17 100 Mbps Serial MII Data Flow ................................................................................................ 134
18 Serial MII Transmit Synchronization ......................................................................................... 135
19 Serial MII Receive Synchronization .......................................................................................... 136
20 Typical SS-SMII Interface ......................................................................................................... 138
21 Typical SS-SMII Quad Sectionalization .................................................................................... 139
22 SS-SMII Transmit Timing ......................................................................................................... 140
23 SS-SMII Receive Timing .......................................................................................................... 140
24 RMII Data Flow ......................................................................................................................... 141
25 Typical RMII Interface............................................................................................................... 142
26 Typical RMII Quad Sectionalization.......................................................................................... 143
27 100BASE-X Frame Format....................................................................................................... 144
28 Protocol Sublayers ................................................................................................................... 145
29 Typical IP Telephone System Connection................................................................................ 151
30 Intel
31 LED Pulse Stretching ............................................................................................................... 157
32 RMII Programmable Out-of-Band Signaling ............................................................................. 157
33 LED Circuit ............................................................................................................................... 167
34 Power and Ground Supply Connections .................................................................................. 168
35 Typical Twisted-Pair Interface .................................................................................................. 169
36 Recommended Intel
37 Recommended Intel
38 ON Semiconductor Triple PECL-to-LVPECL Translator .......................................................... 172
5.3
Test Specifications.................................................................................................................... 173
Register Definitions................................................................................................................... 199
Package Specifications............................................................................................................. 221
8.1
Ordering Information................................................................................................................. 227
Block Diagram ............................................................................................................................ 18
RMII 208-Pin PQFP Assignments .............................................................................................. 20
SMII 208-Pin PQFP Assignments .............................................................................................. 25
SS-SMII 208-Pin PQFP Assignments ........................................................................................ 30
241-Ball BGA23 Assignments (Top View) .................................................................................. 50
196-Ball BGA15 Assignments (Top View) .................................................................................. 98
Interface Signals ....................................................................................................................... 117
Internal Loopback ..................................................................................................................... 119
Management Interface Read Frame Structure ......................................................................... 121
®
5.2.5
5.2.6
Typical Application Circuits............................................................................................... 168
Top Label Marking ............................................................................................................ 226
LXT9785E Negotiation Flow Chart ................................................................................. 155
The Fiber Interface .............................................................................................. 166
LED Circuit........................................................................................................... 167
®
®
LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry...... 170
LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry ......... 171
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
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