KSZ8721SL A4 Micrel Inc, KSZ8721SL A4 Datasheet - Page 12
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KSZ8721SL A4
Manufacturer Part Number
KSZ8721SL A4
Description
Manufacturer
Micrel Inc
Datasheet
1.KSZ8721SL_A4.pdf
(34 pages)
Specifications of KSZ8721SL A4
Lead Free Status / RoHS Status
Compliant
KS8721BL/SL
half-duplex mode (please refer to “Auto-Negotiation”). Auto-negotiation is disabled in the FX mode.
During auto-negotiation, the contents of Register 4, coded in fast link pulse (FLP), are sent to its link partner under the con-
ditions of power-on, link-loss, or restart. At the same time, the KS8721BL/SL monitors incoming data to determine its mode
of operation. The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or 100BASE-TX
idle is detected. The operation mode is configured based on the following priority:
When the KS8721BL/SL receives a burst of FLP from its link partner with three identical link code words (ignoring acknowledge
bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the KS8721BL/SL detects
the second code words, it then configures itself according to the above-mentioned priority. In addition, the KS8721BL/SL also
checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the KS8721BL/SL automatically configures to
match the detected operating speed.
MII Management Interface
The KS8721BL/SL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output
(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721BL/SL. The MDIO
interface consists of the following:
The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status
change on the KS8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register
bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.
MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Control-
ler (MAC) to the KS8721BL/SL, and for receiving data from the line. Normal data transmission is implemented in 4B nibble
mode (4-bit wide nibbles).
Transmit Clock (TXC): The transmit clock is normally generated by the KS8721BL/SL from an external 25MHz reference
source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The
KS8721BL/SL normally samples these signals on the rising edge of the TXC.
Receive Clock (RXC): For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes
down, and auto-negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T
links, the receive clock is recovered from the line while carrier is active, and operates from the master input clock when
the line is idle. The KS8721BL/SL synchronizes the receive data and control signals on the falling edge of RXC in order to
stabilize the signals at the rising edge of the clock with 10ns setup and hold times.
Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN
after the last bit of the packet.
Receive Data Valid: The KS8721BL/SL asserts RXDV when it receives a valid packet. Line operating speed and MII mode
will determine timing changes in the following way:
Error Signals: Whenever the KS8721BL/SL receives an error symbol from the network, it asserts RXER and drives “1110”
(4B) on the RXD pins. When the MAC asserts TXER, the KS8721BL/SL will drive “H” symbols (a Transmit Error defined in
the IEEE 802.3 4B/5B code group) out on the line to force signaling errors.
Carrier Sense (CRS): For 100BASE-TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier
Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair, causes de-assertion of CRS. The PMA layer will also de-as-
sert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS
is de-asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception
M9999-022105
Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
• A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT).
• A specific protocol that runs across the above-mentioned physical connection that allows one controller to com-
• An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions are
• For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last
• For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “5D” and
municate with multiple KS8721BL/SL devices. Each KS8721BL/SL is assigned an MII address between 0 and 31
by the PHYAD inputs.
specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.
nibble of the data packet.
remains asserted until the end of the packet.
12
February 2005
Micrel