L80223/D LSI, L80223/D Datasheet - Page 55
L80223/D
Manufacturer Part Number
L80223/D
Description
Manufacturer
LSI
Datasheet
1.L80223D.pdf
(140 pages)
Specifications of L80223/D
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bits to their default values, and latches in new values for the MI address.
After the power-on reset pulse has finished, the reset bit (RST) in the MI
serial port Control register is cleared and the device is ready for normal
operation.
When reset is initiated because of (3), the same procedure occurs except
the device stays in the reset state as long as the RESETn pin is held
LOW. The RESETn pin has an internal pullup to V
. The device is
DD
guaranteed to be ready for normal operation 50 ms after the reset
sequence is initiated.
2.10 Receive Polarity Correction
In 10 Mbits/s mode, the polarity of the signal on the TP receive input is
continuously monitored.
A start of idle (SOI) pulse is sent at the end of transmission in order to
signal to a receiver that transmission has ended and the idle period has
started. The SOI pulse is a positive pulse. When the SOI pulse is
detected, it indicates that receive data is no longer valid and causes the
device to turn on the receive squelch mechanism. Link pulses are
transmitted occasionally during the idle period.
When the device is powered up, it is assumed that the polarity is correct
and no polarity correction occurs. After that, receive polarity is
continuously monitored by checking the polarity of the SOI pulses (they
are always expected to be positive pulses). If three consecutive SOI
pulses indicate incorrect polarity on the TP receive input, the polarity is
internally determined to be incorrect. In this case, the Reverse Polarity
Detect bit (RPOL) is set in the MI serial port Status Output register.
The device automatically corrects for the reverse polarity condition,
provided the autopolarity feature is not disabled. To disable autopolarity,
set the Autopolarity Disable bit (APOL_DIS) in the MI serial port
Configuration register.
No polarity detection or correction is needed in the 100 Mbits/s mode.
Receive Polarity Correction
2-37
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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