NLXT300ZPE.F4 Intel, NLXT300ZPE.F4 Datasheet - Page 11

• Manufacturer Part Number: NLXT300ZPE.F4
• Manufacturer: Intel

Specifications of NLXT300ZPE.F4

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

2.2.1
2.2.2
2.3
2.3.1
Datasheet
Receive (Loss of Signal) Monitor
The receive monitor generates a Loss of Signal (LOS) output upon receipt of 175 consecutive zeros
(spaces). The receiver monitor loads a digital counter at the RCLK frequency. The count is
incremented each time a zero is received, and reset to zero each time a one (mark) is received.
Upon receipt of 175 consecutive zeros the LOS pin goes High, and the RCLK output is replaced
with MCLK. LOS is reset when the first mark is received.
(In the LXT300Z only, if MCLK is not supplied, the RCLK output will be replaced with the centered
crystal clock.)
Jitter Attenuation (LXT300Z Only)
In the LXT300Z, recovered clock signals are supplied to the jitter attenuator and the data latch. The
recovered data is passed to the elastic store where it is buffered and synchronized with the
dejittered recovered clock (RCLK). Jitter attenuation of the LXT300Z clock and data outputs (see
Figure
crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to
specifications. The ES is a 32 x 2-bit register. Recovered data is clocked into the ES with the
recovered clock signal, and clocked out of the ES with the dejittered clock from the JAL. When the
bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output
clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path.
Transmitter
The transmitter circuits in the LXT300Z and LXT301Z are identical. The following discussion
applies to both devices. Data received for transmission onto the line is clocked serially into the
device at TPOS and TNEG. Input synchronization is supplied by the transmit clock (TCLK). The
transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in
Table
timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the
line at TTIP and TRING. Equalizer Control signals are hard-wired in the LXT301Z.
LXT300Z Only: Equalizer Control signals may be hardwired in the Hardware mode, or input as
part of the serial data stream (SDI) in the Host mode.
Pulses can be shaped for either 1.544 or 2.048 Mbps applications. DSX-1 applications with 1.544
Mbps pulses can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The
LXT300Z and LXT301Z also match FCC specifications for CSU applications. Pulses at 2.048
Mbps can drive coaxial or shielded twisted-pair lines using appropriate resistors in line with the
output transformer.
Driver Performance Monitor
The transceiver incorporates an advanced Driver Performance Monitor (DPM) in parallel with the
TTIP and TRING at the output transformer. The DPM circuitry uses four comparators and a 150 ns
pulse discriminator to filter glitches. The DPM output level goes High upon detection of 63
consecutive zeros, and is cleared when a one is detected on the transmit line, or when a reset
command is received. The DPM output also goes High to indicate a ground on TTIP or TRING. A
ground fault induced DPM flag is automatically cleared when the ground condition is corrected
(chip reset is not required).
4. Refer to the “Test Specifications” section of this data sheet for master and transmit clock
5) is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external
Advanced T1/E1 Short-Haul Transceivers — LXT300Z/LXT301Z
page 18
for crystal
11