OCX256LTB792 Fairchild Semiconductor, OCX256LTB792 Datasheet - Page 8

• Manufacturer Part Number: OCX256LTB792
• Manufacturer: Fairchild Semiconductor

Specifications of OCX256LTB792

• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Mounting: Surface Mount
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: No
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Compliant

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Introduction
0 0 0 0 X
0 0 0 1 X
0 0 1 0 X
0 0 1 1 X
0 1 0 0 X
0 1 0 1 X
0 1 1 0 X
0 1 1 1 X
1 0 0 0 X
1 0 0 1 X
I [3:0]
BB
Select
Clock
BA
X
X
X
X
X
X
X
X
X
(Continued)
Mode
Data
B9
X
X
X
X
X
X
X
X
X
OE OE
B8 B7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Output Address/
Output Buffer
Address
Address
Address
A6 - A0
Output
Output
TABLE 8. JTAG Instructions
Buffer
X
X
X
X
X
X
Sample/EXTEST
Sample/EXTEST
Reset the
Crosspoint Array
Set Array
for
Broadcast mode
Program a Buffer
Configuration
Readback
Update the
Crosspoint Array
Disconnect
Input Cell
Disconnect Input
and Output
Connect with
ImpliedDisconnect
8
Instruction
Places the device in Scan Mode.
Places the device in Scan Mode.
Resets the entire Crosspoint Array to No
Connect. All other Output Buffer configu-
rations are unchanged by this operation.
Use the JTAG Address Register as the
Input address to be the broadcast input
Connects the selected Input to all Output
cells and disconnects all other Inputs.
Activating the Global Update JTAG
instruction returns the Crosspoint array
from the Broadcast mode to the previous
programed state.
Programs the Output Buffer address
specified in the JTAG instruction (A6-A0).
The configuration data is also specified in
the JTAG instruction bits BA-B7. See
Table 11 for bit assignment of the Buffer
functionality.
Readback the connectivity of the Cross-
point cell with the Input location specified
in the JTAG Address Register and the
Output location specified JTAG instruc-
tion (A0-A6). It also returns the configura-
tion of the Output Buffer addressed in the
JTAG instruction (A0-A6).
The readback data is shifted out of TDO
in the following sequence:
1. Crosspoint Connect
2. Output Enable – B7 (see Table 11)
3. Output Enable – B8 (see Table 11)
4. Output Data Source – B9
5. Output Clock Select – BA
6. State of Broadcast bit
7. State of the RCE bit
Note: This instruction does not increment the JTAG
Address Register. This instruction also requires two
DR cycles
Update the programmed connection from
the Loading SRAM to the Active SRAM.
Disconnect the Crosspoint connections
from the Input address specified in the
JTAG Address Register.
Disconnect the Crosspoint cell at the
Input location specified at the JTAG
Address Register and the Output location
specified in the Disconnect JTAG instruc-
tion (A6-A0).
All other connections from the same input
address or to the same output address
remain the same.
Connects the Crosspoint cell at the Input
location specified on the JTAG Address
Register and the output location specified
in the Connect JTAG instruction (A6-A0).
All other connections from the same
Input address or the same Output
address are set to no-connects.
Note: This instruction increments the JTAG Address
Register (Input address).
(1
(0
(0
Connected, 0
Flow-through, 1
Global Clock, 1
Description
No Connection)
Preliminary
Next Neighbor)
registered)