XC6SLX25T-3FGG484C Xilinx Inc, XC6SLX25T-3FGG484C Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
XC6SLX25T-3FGG484C
Manufacturer Part Number
XC6SLX25T-3FGG484C
Description
FPGA Spartan®-6 Family 24051 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Specifications of XC6SLX25T-3FGG484C
Package
484FBGA
Family Name
Spartan®-6
Device Logic Cells
24051
Device Logic Units
15000
Number Of Registers
30064
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
958464
Number Of Logic Elements/cells
24051
Number Of Labs/clbs
1879
Total Ram Bits
958464
Number Of I /o
250
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX25T-3FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 21: GTP Transceiver User Clock Switching Characteristics
Table 22: GTP Transceiver Transmitter Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
Notes:
1.
2.
Symbol
F
F
T
RXREC
T
TXOUT
T
Clocking must be implemented as described in the Spartan-6 FPGA GTP Transceivers User Guide.
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites.
Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
T
T
TXOOBTRANSITION
RX2
TX2
RX
TX
V
TXOOBVDPP
T
Symbol
D
T
D
D
LLSKEW
T
T
D
T
T
T
T
D
J3.125
J3.125
J1.62
J1.25
J1.62
J1.25
J614
J614
RTX
FTX
J2.5
J2.5
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
TX Rise time
TX Fall time
TX lane-to-lane skew
Electrical idle amplitude
Electrical idle transition time
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Description
(2)
(2)
(2)
(2)
(2)
Description
(2)
(2)
(2)
(2)
(2)
(1)
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
Conditions
3.125 Gb/s
Condition
20%–80%
80%–20%
1.62 Gb/s
1.25 Gb/s
614 Mb/s
2.5 Gb/s
(1)
156.25
156.25
320
320
320
160
320
160
80
80
-3
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
156.25
156.25
320
320
320
160
320
160
-3N
Speed Grade
80
80
Typ
140
120
–
–
–
–
–
–
–
–
–
–
–
–
–
67.5
67.5
270
270
270
125
125
270
125
125
-2
Max
0.35
0.15
0.33
0.15
0.20
0.10
0.20
0.10
0.10
0.05
400
20
50
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-1L
–
–
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV
ps
ps
ps
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
15