ISPLSI 5512VE-155LF388 LATTICE SEMICONDUCTOR, ISPLSI 5512VE-155LF388 Datasheet - Page 2

• Manufacturer Part Number: ISPLSI 5512VE-155LF388
• Description: CPLD ispLSI® 5000VE Family 24K Gates 512 Macro Cells 155MHz EECMOS Technology 3.3V 388-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 5512VE-155LF388

• Package: 388FBGA
• Family Name: ispLSI® 5000VE
• Device System Gates: 24000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 8 ns
• Number Of User I/os: 256
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 155 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: 0 to 70 °C

Figure 1. ispLSI 5512VE Functional Block Diagram (256-I/O Option)
Functional Block Diagram
VCCIO
RESET
I/O 12
I/O 13
I/O 14
I/O 15
I/O 28
I/O 29
I/O 30
I/O 31
I/O 44
I/O 45
I/O 46
I/O 47
1 TOE
I/O 16
I/O 17
I/O 18
I/O 19
I/O 32
I/O 33
I/O 34
I/O 35
I/O 60
I/O 61
I/O 62
I/O 63
I/O 48
I/O 49
I/O 50
I/O 51
I/O 1
I/O 2
I/O 3
1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Use the table below to determine which I/O
is shared by package type.
Logic Block
Logic Block
Generic
Input Bus
Generic
Input Bus
Package Type
256 fpBGA
272 BGA
388 fpBGA
388 BGA
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
I/O 119 / CLK2
I/O 119 / CLK2
I/O 179 / CLK2
I/O 179 / CLK2
Global Routing Pool
Multiplexed Signals
(GRP)
I/O 131 / CLK 3
I/O 197 / CLK 3
I/O 197 / CLK 3
I/O 131 / CLK3
2
Logic Block
Logic Block
Specifications ispLSI 5512VE
Generic
Generic
Input Bus
Input Bus
I/O 0 / TOE
I/O 0 / TOE
I/O 0 / TOE
I/O 0 / TOE
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
Boundary
Interface
Scan
TDI
TDO
I/O 191
I/O 190
I/O 189
I/O 188
I/O 179
I/O 178
I/O 177
I/O 176
I/O 175/CLK3
I/O 174
I/O 173
I/O 172
I/O 163
I/O 162
I/O 161
I/O 160
I/O 159/CLK2
I/O 158
I/O 157
I/O 156
I/O 147
I/O 146
I/O 145
I/O 144
I/O 143
I/O 142
I/O 141
I/O 140
I/O 131
I/O 130
I/O 129
I/O 128