ISPLSI 5512VE-155LF388 LATTICE SEMICONDUCTOR, ISPLSI 5512VE-155LF388 Datasheet - Page 17

• Manufacturer Part Number: ISPLSI 5512VE-155LF388
• Description: CPLD ispLSI® 5000VE Family 24K Gates 512 Macro Cells 155MHz EECMOS Technology 3.3V 388-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 5512VE-155LF388

• Package: 388FBGA
• Family Name: ispLSI® 5000VE
• Device System Gates: 24000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 8 ns
• Number Of User I/os: 256
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 155 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: 0 to 70 °C

1
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for
details.
Routing Adders
Tioi Input Adders
Tioo Output Adders
Tbla Additional Block Loading Adders
ispLSI 5512VE Timing Parameters (continued)
LVCMOS25_out
LVCMOS33_out
Timing for open drain configurations is the same as non-open drain configurations.
ADDER TYPE
Slow Slew I/O
LVTTL_out
clk1
clk2
clk3
t
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
lp
BASE PARAMETER
1
t
t
t
buf,
buf,
buf,
t
t
t
t
buf,
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
gclk_in
gclk_in
gclk_in
route
route
route
route
route
route
route
route
route
route
route
route
route
route
route
route
t
t
t
en,
en,
en,
t
en
t
t
t
dis
dis
dis
-155
1.0
1.5
1.5
1.5
0.1
0.2
0.2
0.3
0.4
0.5
0.6
0.6
0.7
0.8
0.9
1.0
1.0
1.1
1.2
4.0
0.0
0.5
0.0
17
Specifications ispLSI 5512VE
-125
1.5
1.7
1.7
1.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
4.0
0.0
0.5
0.0
ADDER
-100
1.5
1.7
1.7
1.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
4.0
0.0
0.5
0.0
-80
1.5
1.7
1.7
1.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
4.0
0.0
0.5
0.0
Timing Table/5512VE
Timing v.2.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns