ISPLSI 5512VE-155LF388 LATTICE SEMICONDUCTOR, ISPLSI 5512VE-155LF388 Datasheet - Page 12

• Manufacturer Part Number: ISPLSI 5512VE-155LF388
• Description: CPLD ispLSI® 5000VE Family 24K Gates 512 Macro Cells 155MHz EECMOS Technology 3.3V 388-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 5512VE-155LF388

• Package: 388FBGA
• Family Name: ispLSI® 5000VE
• Device System Gates: 24000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 8 ns
• Number Of User I/os: 256
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 155 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: 0 to 70 °C

1. I/O voltage configuration must be set to VCC.
3-state levels are measured 0.5V from
steady-state active level.
Output Load Conditions (See Figure 9)
V
V
V
V
V
SYMBOL
Switching Test Conditions
A
B
C
D
DC Electrical Characteristics for 3.3V Range
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
TEST CONDITION
CCIO
IL
IH
OL
OH
Active High
Active Low
Active High to Z
at V -0.5V
Active Low to Z
at V +0.5V
Slow Slew
OH
OL
I/O Reference Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
316Ω
316Ω
316Ω
R1
PARAMETER
∞
∞
∞
3.3V
348Ω
348Ω
348Ω
R2
∞
∞
∞
Over Recommended Operating Conditions
≤ 1.5ns 10% to 90%
511Ω
511Ω
511Ω
GND to V
R1
∞
∞
∞
See Figure 9
2.5V
1.5V
1.5V
Table 2-0004A/5KVE
475Ω
475Ω
475Ω
R2
Table 2-0003/5KVE
∞
∞
∞
CCIO min
35pF
35pF
35pF
35pF
5pF
5pF
CL
V
V
CCIO = min
CCIO = min
12
1
Figure 9. Test Load
*
Device
Output
Specifications ispLSI 5512VE
C L includes Test Fixture and Probe Capacitance.
, I
, I
CONDITION
OL
OH
= 8 mA
= -4 mA
V
CCIO
MIN.
-0.3
R 1
R 2
3.0
2.0
2.4
–
TYP.
–
–
–
–
–
C L
*
MAX. UNITS
5.25
3.6
0.8
0.4
–
Table 2-0007/5KVE
Point
Test
0213D
V
V
V
V
V