ZY7010L-T1 POWER ONE, ZY7010L-T1 Datasheet - Page 27

• Manufacturer Part Number: ZY7010L-T1
• Description: Module DC-DC 1-OUT 0.5V to 5.5V 10A 25-Pin SMT T/R
• Manufacturer: POWER ONE
• Type: Step Downr

Specifications of ZY7010L-T1

• Package: 25SMT
• Output Current: 10 A
• Output Voltage: 0.5 to 5.5 V
• Input Voltage: 3 to 13.2 V
• Number Of Outputs: 1
• Switching Regulator: Yes

Figure 50 shows the input voltage noise of the three-
output system with programmed interleave. Instead
of all three POLs switching at the same time as in
the previous example, the POLs V1, V2, and V3
switch at 67.5°, 180°, and 303.75°, respectively.
Noise is spread evenly across the switching cycle
resulting in more than 1.5 times reduction.
achieve similar noise reduction without the interleave
will require the addition of an external LC filter.
Similar noise reduction can be achieved on the
output of POLs connected in parallel. Figure 51 and
Figure 52 show the output noise of two ZY7010Ls
connected in parallel without and with 180°
interleave, respectively. Resulting noise reduction is
more than 2 times and is equivalent to doubling
switching frequency or adding extra capacitance on
the output of the POLs.
ZD-00422 Rev. 2.5, 01-Jul-10
Figure 51. Output Voltage Noise, Full Load, No Interleave
Figure 50. Input Voltage Noise with Interleave
www.power-one.com
ZY7010L 10A DC-DC Intelligent POL Data Sheet
To
3V to 13.2V Input
The ZY7010L interleave feature is similar to that of
multiphase converters, however, unlike in the case of
multiphase converters, interleave does not have to
be equal to 360/N, where N is the number of POLs in
a system. ZY7010L interleave is independent of the
number of POLs in a system and is fully
programmable in 11.25 steps. It allows maximum
output noise reduction by intelligently spreading
switching energy.
Note: Due to noise sensitivity issues that may occur in limited
8.4.3
The ZY7010L is a step-down converter therefore
V
between the two parameters is characterized by the
duty cycle and can be estimated from the following
equation:
Where, DC is the duty cycle, V
maximum output voltage (including margining),
V
It is good practice to limit the maximum duty cycle of
the PWM controller to a somewhat higher value
compared to the steady-state duty cycle as
expressed by the above equation. This will further
protect the output from excessive voltages. The duty
cycle limit can be programmed in the GUI PWM
Controller window or directly via the I
writing into the DCL register shown in Figure 53.
Figure 52. Output Voltage Noise, Full Load, 180 Interleave
OUT
IN.MIN
cases, it is recommended to avoid phase lag settings of
112.5 and 123.75 degrees, otherwise false PG and/or OV
indications may occur.
is always less than V
is the minimum input voltage.
Duty Cycle Limit
DC


0.5V to 5.5V Output
V
V
IN
OUT
.
MIN
IN
.
,
Page 27 of 34
OUT
The relationship
is the required
2
C bus by