STS12NH3LL STMicroelectronics, STS12NH3LL Datasheet

MOSFET N-CH 30V 12A 8-SOIC

STS12NH3LL

Manufacturer Part Number
STS12NH3LL
Description
MOSFET N-CH 30V 12A 8-SOIC
Manufacturer
STMicroelectronics
Series
STripFET™r
Datasheet

Specifications of STS12NH3LL

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
10.5 mOhm @ 6A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
12A
Vgs(th) (max) @ Id
1V @ 250µA
Gate Charge (qg) @ Vgs
12nC @ 4.5V
Input Capacitance (ciss) @ Vds
965pF @ 25V
Power - Max
2.7W
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4122-2

Available stocks

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Part Number:
STS12NH3LL
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STS12NH3LL
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Part Number:
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Features
Application
Description
This series is based on the latest generation of
ST’s proprietary “STripFET™” technology. An
innovative layout enables the device to also
exhibit extremely low gate charge for the most
demanding requirements as high-side switch in
high-frequency DC-DC converters. It’s therefore
ideal for high-density converters in telecom and
computer applications.
Table 1.
November 2007
STS12NH3LL
Optimal R
Switching losses reduced
Low input capacitance
Low threshold device
Switching applications
STS12NH3LL
Type
Order code
Device summary
DS(on)
x Qg trade-off @ 4.5 V
V
30 V
DSS
ultra low gate charge STripFET™ Power MOSFET
<0.0105 Ω
R
DS(on)
Marking
12H3LL
12 A
N-channel 30 V - 0.008 Ω - 12 A - SO-8
I
D
Rev 9
Figure 1.
Packag
SO-8
Internal schematic diagram
STS12NH3LL
SO-8
Tape & reel
Packaging
www.st.com
1/13
13

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STS12NH3LL Summary of contents

Page 1

... DC-DC converters. It’s therefore ideal for high-density converters in telecom and computer applications. Table 1. Device summary Order code STS12NH3LL November 2007 N-channel 0.008 Ω SO DS(on Figure 1. Marking Packag 12H3LL Rev 9 STS12NH3LL SO-8 Internal schematic diagram Packaging SO-8 Tape & reel 1/13 www.st.com 13 ...

Page 2

... Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/ STS12NH3LL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ...

Page 3

... STS12NH3LL 1 Electrical ratings Table 2. Absolute maximum ratings Symbol V Drain-source voltage (V DS (1) V Gate-source voltage GS (2) V Gate-source voltage GS I Drain current (continuous Drain current (continuous (3) I Drain current (pulsed Total dissipation at T TOT T Operating junction temperature J Storage temperature T stg 1. Continuous mode 2. Guaranteed for test time ≤ ...

Page 4

... 4 Parameter Test conditions V = =25 V, f=1 MHz = =4 (see Figure 20) gate-to-source gate-to-source (see Figure 20) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain STS12NH3LL Min. Typ 250 µ 0.008 0.0105 0.010 0.013 D Min. Typ. Max 965 285 3 2.5 D 1.2 0.5 1.5 Max ...

Page 5

... STS12NH3LL Table 6. Switching times Symbol t d(on) Turn-on delay time t Rise time r t Turn-off delay time d(off) Fall time t f Table 7. Source drain diode Symbol I Source-drain current SD (1) Source-drain current (pulsed) I SDM (2) Forward on Voltage Reverse recovery time rr Q Reverse recovery charge rr Reverse recovery current ...

Page 6

... Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 4. Output characteristics Figure 6. Transconductance 6/13 Figure 3. Thermal impedance Figure 5. Transfer characteristics Figure 7. Static drain-source on resistance STS12NH3LL ...

Page 7

... STS12NH3LL Figure 8. Gate charge vs gate-source voltage Figure 9. Figure 10. Normalized gate threshold voltage vs temperature Figure 12. Source-drain diode forward characteristics Electrical characteristics Capacitance variations Figure 11. Normalized on resistance vs temperature Figure 13. Normalized B VDSS vs temperature 7/13 ...

Page 8

... Test circuit Figure 14. Switching times test circuit for resistive load Figure 16. Test circuit for inductive load switching and diode recovery times Figure 18. Unclamped inductive waveform 8/13 Figure 15. Gate charge test circuit Figure 17. Unclamped inductive load test circuit Figure 19. Switching time waveform STS12NH3LL ...

Page 9

... STS12NH3LL Figure 20. Gate charge waveform Vds Vgs(th) Qgs1 Qgs2 Qgd Id Vgs Test circuit 9/13 ...

Page 10

... These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: 10/13 www.st.com STS12NH3LL ...

Page 11

... STS12NH3LL DIM SO-8 MECHANICAL DATA mm. MIN. TYP MAX. 1.75 0.1 0.25 1.65 0.65 0.85 0.35 0.48 0.19 0.25 0.25 0.5 45 (typ.) 4.8 5.0 5.8 6.2 1.27 3.81 3.8 4.0 0.4 1.27 0.6 8 (max.) Package mechanical data inch MIN. TYP. MAX. 0.068 ...

Page 12

... Revision 1 First release 2 Some value change in 3 Complete version 4 Ron value change (see 5 New Rg value on Table 5 6 The document has been reformatted 7 New parameters on Table 5 8 Modified value on Table 2 9 Modified marking on Table 1 STS12NH3LL Changes Table 2 Table 4) and new Figure 20 ...

Page 13

... STS12NH3LL Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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