78Q2120C-64CGTR/F Maxim Integrated Products, 78Q2120C-64CGTR/F Datasheet
78Q2120C-64CGTR/F
Related parts for 78Q2120C-64CGTR/F
78Q2120C-64CGTR/F Summary of contents
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... DESCRIPTION The 78Q2120C is a 10BASE-T/100BASE-TX Fast Ethernet transceiver. It includes integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation function. The transmitter includes an on-chip pulse-shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver ...
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... Hence only a single Vcc supply is required to power-up the device. regulator is not affected by the power-down mode. Clock Selection The 78Q2120C will use the on-chip crystal oscillator as the clock source if the CKIN pin is tied low. In this Page mode of operation, a 25MHz crystal should be connected between the XTLP and XTLN pins. ...
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... Polarity Correction The 78Q2120C is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Register bits MR16.5 and MR16.4 control this feature. The default is automatic mode where MR16.5 is low and MR16.4 indicates if the detection circuitry has inverted the input signal ...
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... RXD[3:0] pins. The natural loopback function is enabled through register bit MR16.10. Repeater Mode When the RPTR pin is high or register bit MR16.15 is set, the 78Q2120C is placed in repeater mode. In this mode, full duplex operation is prohibited, CRS responds only to receive activity and, in 10BASE-T mode, the SQE test function is disabled. ...
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... Interrupt Pin The 78Q2120C has an Interrupt pin (INTR) that is asserted whenever any of the eight interrupt bits of MR17.7:0 are set. disabled via the MR17.15:8 Interrupt Enable bits. The Interrupt Polarity bit, MR16.14, controls the active level of the INTR pin ...
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... TX_EN is high. In PCS bypass mode this pin becomes the MSB of the transmit 5-bit code group. CARRIER SENSE: When the 78Q2120C is not in repeater mode, CRS is high whenever a non-idle condition exists on either the transmitter or the receiver. In repeater mode, CRS is only active when a non-idle condition exists on the receiver ...
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... MII register bit (MR0.15) POWER-DOWN: The 78Q2120C may be placed in a low power consumption state by setting this signal to logic high. While in the power-down state, the 78Q2120C still responds to management transactions. state can also be activated using the PWRDN bit in the MII register (MR0.11). ...
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... ISOLATE: When set to logic one, the 78Q2120C will present a high impedance on its MII output pins. attached to the same MII interface. When the 78Q2120C is isolated, it still responds to management transactions. This high impedance state can also be achieved using the ISO bit in the MII register (MR0.10). ...
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... INPOL bit (MR16.14). The events which trigger an interrupt can be programmed via the Interrupt Control Register located at address MR17. No Connect. Do not connect to ground or supply. DESCRIPTION 3.3V SUPPLY GROUND © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver Rev 1.3 ...
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... Attempts to read unsupported registers will be ignored and the MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those which are unique to the 78Q2120C, will respond to the broadcast PHYAD value of ‘00000’. The registers specific to the 78Q2120C occupy address space MR16-22. ...
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... Speed Selection: This bit determines the speed of operation of the 78Q2120C. Setting this bit to ‘1’ indicates 100Base-TX operation and a ‘0’ indicates 10Base-T mode. This bit will default to a ‘1’ upon reset. If the TECH[2:0] pins are all logic zero and auto-negotiation is not enabled, this bit will be writeable ...
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... RSVD R MR1: Status Register Bits 1.15 through 1.11 reflect the ability of the 78Q2120C as configured by the TECH[2:0] pins. They do not reflect any ability changes made via the MII Management interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX). BIT SYMBOL TYPE DEFAULT DESCRIPTION 1 ...
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... DESCRIPTION 1Ch Organizationally Unique Identifier: Remaining 6 bits of the OUI. 0Ch Model Number: The last 2 digits of the model number 78Q2120C are encoded into the 6 bits. 9h Revision Number: The value ‘1001’ corresponds to the ninth revision of the silicon. © ...
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... Reserved for future technology. 0 Reserved 0 Reserved. 0 100BASE-T4: The 78Q2120C does not support 100BASE-T4 operation. (1) 100BASE-TX Full Duplex: If the MR1.14 bit is ‘1’, this bit will be set to ‘1’ upon reset and will be writeable. Otherwise, this bit cannot be set to ‘1’ by the management. (1) 100BASE-TX: If the MR1.13 bit is ‘ ...
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... Link Partner Next Page Able: When ‘1’ is read, it indicates the link partner supports the Next Page function. 0 Next Page Able: Reads ‘0’ since the 78Q2120C does not support Next Page function. 0 Page Received: Reads ‘1’ when a new link code word has been received into the Auto-Negotiation Link Partner Ability Register ...
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... When the reverse polarity is detected and if the Auto Polarity feature is enabled, the 78Q2120C will invert the receive data input and set this bit to ‘1’. If Auto Polarity is disabled, then this bit is writeable. Writing a ‘1’ to this bit forces the polarity of the receive signal to be reversed. ...
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... Page Received Interrupt: This bit is set high when a new page has been received from the link partner during auto-negotiation. 0 Parallel Detect Fault Interrupt: This bit is set high by the auto- negotiation logic when a parallel detect fault condition is indicated. © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver Rev 1.3 ...
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... Reserved: Must set to ‘00h’. © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver This bit is set when the link This bit is set when a remote fault This bit is set when auto- In 10Base-T mode, this bit Rev 1 ...
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... Gain set for 0.0dB of insertion loss 01 : Gain set for 0.4dB of insertion loss 10 : Gain set for 0.8dB of insertion loss 11 : Gain set for 1.2dB of insertion loss XXXh Reserved XXXXh Reserved XXXXh Reserved XXXXh Reserved © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver Rev 1.3 ...
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... VDC ± 120 mA RATING 3.3 ± 0.3 VDC 0 to +70°C 125°C 45°C/W CONDITIONS MIN Vcc = 3.3V; Auto-Negotiation 10BT (Idle) 10BT (Normal Activity) 100BTX Power-down mode © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver NOM MAX UNIT 110 88 110 5 mA ...
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... C = 20pF L Iz SYMBOL CONDITIONS Vol Iol = 8mA Voh Ioh = -8mA 20pF L SYMBOL CONDITIONS Vol Iol = 4mA Voh Ioh = -4mA 20pF L © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver MIN NOM MAX UNIT 0.8 2.0 5 µ kΩ kΩ MIN NOM MAX UNIT 1 ...
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... DIGITAL TIMING CHARACTERISTICS RST Characteristics VCC Oscillator RST PARAMETER SYMBOL RST Pulse Assertion Page reset RST Pulse Duration CONDITIONS Treset VCC = 3.3V and oscillator stabilized © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver MIN NOM MAX UNIT 30 Oscillator Clock Cycles Rev 1.3 ...
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... RX_CLK Duty-Cycle RX_CLK RXD[3:0] RX_DV or RX_ER Page CONDITIONS CKIN T CKIN CKIN TX SU TX_CLK TXD[3:0] TX_EN or TX_ER Transmit Inputs to the 78Q2120C CONDITIONS RX DLY RX DLY (MAX) RX DLY (MIN) Receive Outputs from the 78Q2120C © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver MIN NOM MAX ...
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... Z after MDC MDC MCZ2D MDIO Page CONDITIONS MIO SU MIO HD F max MDC MIO HD MIO SU MDIO MDIO as an Input to the 78Q2120C CONDITIONS MC2D MC2D MDIO as an Output from the 78Q2120C © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver MIN NOM MAX ...
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... MDIO Interface Output Timing Page © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver Rev 1.3 ...
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... SQE test wait SQE test duration Jabber on-time* Jabber off-time* * Guarantee by design. The specifications in the following table are included for information only. Page CONDITION RPTR = low RPTR = low CONDITION MIN 20 250 © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver NOM UNIT ...
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... Deviation from best-fit time-grid; 010101... Sequence Scrambled Idle TLA-6T103 100Ω ±1% CONDITION 2 < f < 30 MHz 30 < f < 60 MHz − < f < 80 MHz -8 < Iin < © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver NOM MAX UNIT 1050 mVpk 1. 500 ps ±250 ps 1 ...
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... Not tested Not tested CONDITION MIN All data patterns 2.2 All ones data 27 Not tested Last bit 0 Last bit 1 TLA-6T103 100Ω ±1% © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver NOM MAX UNIT 600 700 mVppd 350 425 mVppd 20 kΩ ns ...
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... V , 10.1 MHz sine pk wave applied to transmitter common- mode. All data sequences. CONDITION MIN 30 500 275 Square wave 25 0 < f < 500 kHz Not tested © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver NOM MAX UNIT 100 ...
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... R4 R5 TLA-6T103 R16 49.9 49.9 TDK SMT16 R17 R18 0603 0603 75 75 C11 VCC 0.01 1.5KV C6 C5 1808 0.1 0.01 Note 2: This application circuit is only valid for the 78Q2120C09 revision. Refer to Ordering Information for revision identification. 78Q2120C RJ45 CGND Rev 1.3 ...
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... VALUE 25.00000 4** ±50 ±2 ±5 Parallel Resonance, Fundamental Mode 50 - 100 > below main within 500 kHz © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver This table gives the recommended line CONDITION @ 10 mV, 10 kHz @ 1 MHz (min MHz UNITS MHz pF PPM PPM/yr PPM µW ...
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... Note 1: IEEE 802.3 frequency tolerance ±50 ppm Page CKIN T clkper T clkhi External CKIN Oscillator Characteristics CONDITION See Note 1 See Note 1 Tclkhi / Tclkper Input signaling requirements = CI © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver MIN NOM MAX 25.000 4.0 0.1 UNIT MHz Rev 1.3 ...
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... PWRDN VCC GND GND VCC PHYAD4 PHYAD3 PHYAD2 PHYAD1 PHYAD0 Page 78Q2120C © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver LEDBT LEDBT LEDBT ANEGA ANEGA ANEGA TECH0 TECH0 TECH0 TECH1 TECH1 TECH1 TECH2 TECH2 TECH2 VCC VCC VCC GND GND GND ...
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... PIN No. 1 Indicator 0.60 (0.024) Typ. Page 11.7 (0.460) 12.3 (0.484) 9.8 (0.386) 10.2 (0.402) 0.14 (0.006) 0.50 (0.0197) Typ. 0.28 (0.011) © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver 0.00 (0) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) Rev 1.3 ...
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... ORDERING INFORMATION PART DESCRIPTION 78Q2120C (Revision 9) 64-pin LQFP 78Q2120C (Revision 9) 64-pin LQFP - Lead Free REVISION HISTORY Rev. # Date 1.0 September 2004 1.1 January 2005 1.2 August 2005 1.3 January 2009 No responsibility is assumed by Teridian Semiconductor Corporation for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use ...