CY62128ELL-45ZAXIT Cypress Semiconductor Corp, CY62128ELL-45ZAXIT Datasheet - Page 8

CY62128ELL-45ZAXIT

CY62128ELL-45ZAXIT

Manufacturer Part Number
CY62128ELL-45ZAXIT
Description
CY62128ELL-45ZAXIT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62128ELL-45ZAXIT

Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (128K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-sTSOP
Density
1Mb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
STSOP-I
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
16mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62128ELL-45ZAXIT
Manufacturer:
CYPRESS
Quantity:
780
Switching Waveforms
Document #: 38-05485 Rev. *H
Notes
24. CE is the logical combination of CE
25. The internal Write time of the memory is defined by the overlap of WE, CE = V
26. Data I/O is high impedance if OE = V
27. If CE
28. During this period, the I/Os are in output state and input signals must not be applied.
ADDRESS
ADDRESS
DATA I/O
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
DATA I/O
1
goes HIGH or CE
WE
WE
CE
CE
NOTE 28
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
t
SA
Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled)
1
(continued)
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)
and CE
IH
.
t
HZWE
2
. When CE
t
SA
1
is LOW and CE
t
AW
t
AW
t
SCE
t
t
WC
2
WC
t
is HIGH, CE is LOW; when CE
PWE
IL
t
. All signals must be ACTIVE to initiate a write and any of these signals can
PWE
t
DATA VALID
DATA VALID
t
SCE
SD
t
SD
[24, 25, 26, 27]
1
is HIGH or CE
[24, 27]
t
HD
t
t
HA
LZWE
t
HA
t
HD
2
is LOW, CE is HIGH.
CY62128E MoBL
Page 8 of 14
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