ADSP-21065LKCAZ264 Analog Devices Inc, ADSP-21065LKCAZ264 Datasheet - Page 33
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ADSP-21065LKCAZ264
Manufacturer Part Number
ADSP-21065LKCAZ264
Description
ADSP-21065L 66MHZ MINI BGA
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet
1.ADSP-21065LKSZ-240.pdf
(44 pages)
Specifications of ADSP-21065LKCAZ264
Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
196-CSPBGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
66MHz
Mips
66
Device Input Clock Speed
66MHz
Ram Size
68KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21065LKCAZ264
Manufacturer:
Analog Devices Inc
Quantity:
10 000
REV. C
TFS ("LATE", EXT.)
TFS ("LATE", INT.)
DATA RECEIVE– INTERNAL CLOCK
DATA TRANSMIT– INTERNAL CLOCK
RCLK
TCLK
RFS
TFS
DR
DT
TCLK (EXT)
TCLK (INT)
DRIVE
DRIVE
EDGE
EDGE
DT
DT
t
t
HOFSE
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
HOFSI
HDTI
t
DFSE
t
t
DRIVE
EDGE
DRIVE
DFSI
EDGE
DDTI
t
t
DDTIN
DDTEN
t
t
SCLKIW
SCLKIW
t
TFS, RFS, DT
t
t
TCLK, RCLK
SFSI
SFSI
SDRI
RCLK (INT)
TCLK (INT)
CLKIN
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HFSI
HDRI
HFSI
SPORT DISABLE DELAY
FROM INSTRUCTION
Figure 20. Serial Ports
LOW TO HIGH ONLY
t
DCLK
t
DPTR
–33–
TCLK / RCLK
TCLK / RCLK
DATA RECEIVE– EXTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
RCLK
TCLK
RFS
TFS
DR
DT
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
DRIVE
DRIVE
EDGE
EDGE
t
t
t
HOFSE
HOFSE
DRIVE
DRIVE
EDGE
EDGE
HDTE
t
t
t
DFSE
DFSE
DDTTI
t
t
DDTE
DDTTE
t
t
SCLKW
SCLKW
t
t
t
SFSE
SDRE
SFSE
ADSP-21065L
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HFSE
HDRE
HFSE