ADSP-21065LKCAZ264 Analog Devices Inc, ADSP-21065LKCAZ264 Datasheet - Page 22
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ADSP-21065LKCAZ264
Manufacturer Part Number
ADSP-21065LKCAZ264
Description
ADSP-21065L 66MHZ MINI BGA
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet
1.ADSP-21065LKSZ-240.pdf
(44 pages)
Specifications of ADSP-21065LKCAZ264
Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
196-CSPBGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
66MHz
Mips
66
Device Input Clock Speed
66MHz
Ram Size
68KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21065LKCAZ264
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21065L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21065Ls (BRx) or a host processor (HBR,
HBG).
Parameter
Timing Requirements:
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
For first asynchronous access after HBR and CS asserted, ADDR
Only required for recognition in the current cycle.
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
(O/D) = open drain, (A/D) = active drive.
HBGRCSV
SHBRI
HHBRI
SHBGI
HHBGI
SBRI
HBRI
DHBGO
HHBGO
DBRO
HBRO
DCPAO
TRCPA
DRDYCS
TRDYHG
ARDYTR
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the
ADSP-21065L SHARC User’s Manual, Second Edition.
HBG Low to RD/WR/CS Valid
HBR Setup Before CLKIN
HBR Hold Before CLKIN
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
BRx, CPA Setup Before CLKIN
BRx, CPA Hold Before CLKIN High
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS and HBR Low
REDY (O/D) Disable or REDY (A/D) High from HBG
REDY (A/D) Disable from CS or HBR High
2
2
1
3
23-0
must be a nonMMS value 1/2 t
4
–22–
4
4
CK
before RD or WR goes low or by t
Min
12.0 + 12 DT
6.0 + 8 DT
7.0 + 8 DT
1.0 – 2 DT
1.0 – 2 DT
1.0 – 2 DT
44.0 + 43 DT
Max
20.0 + 36 DT
6.0 + 12 DT
1.0 + 8 DT
1.0 + 8 DT
8.0 – 2 DT
7.0 – 2 DT
11.5 – 2 DT
5.5 – 2 DT
13.0
10.0
HBGRCSV
after HBG goes
REV. C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns