AD9833BRM Analog Devices Inc, AD9833BRM Datasheet - Page 6

• Manufacturer Part Number: AD9833BRM
• Description: 10 Bit, 10 Pin DDS
• Manufacturer: Analog Devices Inc

Specifications of AD9833BRM

• Rohs Status: RoHS non-compliant
• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 28 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution: 10 Bit
• Maximum Input Frequency: 25 MHz
• Tuning Word Width: 28 Bit
• Minimum Operating Supply Voltage: 2.3 V
• Typical Operating Supply Voltage: 2.5|3.3|5 V
• Maximum Operating Supply Voltage: 5.5 V
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 105 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD9833EBZ - BOARD EVAL FOR AD9833
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9833
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
COMP
VDD
CAP/2.5 V
DGND
MCLK
SDATA
SCLK
FSYNC
AGND
VOUT
Description
A DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
Positive Power Supply for the Analog and the Digital Interface Sections. The on-board 2.5 V regulator is also
supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 µF and a 10 µF decoupling capacitor should
be connected between VDD and AGND.
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board
regulator (when VDD exceeds 2.7 V). The regulator requires a decoupling capacitor of typically 100 nF, which is
connected from CAP/2.5 V to DGND. If VDD is equal to or less than 2.7 V, CAP/2.5 V should be tied directly to VDD.
Digital Ground.
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
Serial Data Input. The 16-bit serial data-word is applied to this input.
Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low,
the internal logic is informed that a new word is being loaded into the device.
Analog Ground.
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor
is not required because the device has a 200 Ω resistor on board.
CAP/2.5V
COMP
DGND
MCLK
VDD
Figure 5. Pin Configuration
Rev. C | Page 6 of 24
1
2
3
4
5
(Not to Scale)
AD9833
TOP VIEW
10
9
8
7
6
VOUT
AGND
FSYNC
SCLK
SDATA