LC4064ZE-EVN Lattice, LC4064ZE-EVN Datasheet - Page 34
LC4064ZE-EVN
Manufacturer Part Number
LC4064ZE-EVN
Description
MCU, MPU & DSP Development Tools ispMACH4064ZE Eval board
Manufacturer
Lattice
Datasheet
1.LC4064ZE-5TN100C.pdf
(60 pages)
Specifications of LC4064ZE-EVN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
ispMACH 4000ZE Power Supply and NC Connections
VCC
VCCO0
VCCO (Bank 0)
VCCO1
VCCO (Bank 1)
GND
GND (Bank 0)
GND (Bank 1)
NC
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
4. All bonded grounds are connected to the following two balls, D4 and E5.
the bank shown.
ascending horizontally.
Signal
12, 36
6
30
13, 37
5
29
—
48 TQFP
2
E4, D5
4032ZE: E3
4064ZE: E3, F4
4032ZE: D6
4064ZE: D6, C6
D4, E5
D4, E5
D4, E5
—
64 csBGA
34
3, 4
ispMACH 4000ZE Family Data Sheet
E4, D5
C3, F3
F6, A6
D4, E5
D4, E5
D4, E5
—
64 ucBGA
1
3, 4
25, 40, 75, 90
13, 33, 95
45, 63, 83
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
—
100 TQFP
2
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