71M6512-DB Maxim Integrated Products, 71M6512-DB Datasheet - Page 127
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71M6512-DB
Manufacturer Part Number
71M6512-DB
Description
Power Management Modules & Development Tools 71M6512 DEMO BOARD 71M6512 DEMO BOARD
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6521DE-DB.pdf
(138 pages)
- Current page: 127 of 138
- Download datasheet (2Mb)
71M652X Software User’s Guide
Refreshing the WD Timer
The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This re-
quirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the
second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this
period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded
with the content of the WDTREL register and WDT is automatically reset.
Note: The remaining bits in the IEN1 register are not used for watchdog control
Interrupt Priority 0 Register (IP0):
Revision 1.7
IEN0.6
IEN1.6
Bit
Bit
Bit
Interrupt Enable 0 Register (IEN0):
Interrupt Enable 1 Register (IEN1):
Note: The remaining bits in the IEN0 register are not used for watchdog control
Special Function Registers for the WD Timer
MSB
MSB
MSB
EXEN2
OWDS
EALl
Symbol
Symbol
Symbol
SWDT
WDT
SWDT
WDTS
WDT
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is
set to prevent an unintentional refresh of the watchdog timer. WDT is reset by
hardware 12 clock cycles after it has been set.
Function
Watchdog timer start/refresh flag.
Set to activate/refresh the watchdog timer. When directly set after setting WDT, a
watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock
cycles after it has been set.
Function
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
IP0.5
EX6
ET2
Table 6-34: The IEN0 Bit Functions
Table 6-36: The IEN1 Bit Functions
Table 6-33: The IEN0 Register
Table 6-35: The IEN1 Register
Table 6-37: The IP0 Register
IP0.4
TERIDIAN Proprietary
ES0
EX5
IP0.3
ET1
EX4
IP0.2
EX1
EX3
IP0.1
EX2
ET0
IP0.0
EX0
LSB
LSB
LSB
127 of 138
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