EVAL-ADXL346Z Analog Devices Inc, EVAL-ADXL346Z Datasheet - Page 27

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EVAL-ADXL346Z

Manufacturer Part Number
EVAL-ADXL346Z
Description
Inertial Sensor Evaluation System
Manufacturer
Analog Devices Inc
Datasheets

Specifications of EVAL-ADXL346Z

Silicon Manufacturer
Analog Devices
Silicon Core Number
ADXL346
Kit Application Type
Sensing - Motion / Vibration / Shock
Application Sub Type
Accelerometer
Silicon Family Name
IMEMS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register 0x39—FIFO_STATUS (Read Only)
D7
FIFO_TRIG
FIFO_TRIG Bit
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
and a 0 means that a FIFO trigger event has not occurred.
Entries Bits
These bits report how many data values are stored in FIFO.
Access to collect the data from FIFO is provided through the
DATAX, DATAY, and DATAZ registers. FIFO reads must be
done in burst or multiple-byte mode because each FIFO level is
cleared after any read (single- or multiple-byte) of FIFO. FIFO
stores a maximum of 32 entries, which equates to a maximum
of 33 entries available at any given time because an additional
entry is available at the output filter of the device.
Register 0x3A—TAP_SIGN (Read Only)
D7
0
xSIGN Bits
These bits indicate the sign of the first axis involved in a tap
event. A setting of 1 corresponds to acceleration in the negative
direction, and a setting of 0 corresponds to acceleration in the
positive direction. These bits update only when a new single-
tap/double-tap event is detected, and only the axes enabled in the
TAP_AXES register (Address 0x2A) are updated. The TAP_SIGN
register should be read before clearing the interrupt. See the Tap
Sign section for more details.
xTAP Bits
These bits indicate the first axis involved in a tap event. A
setting of 1 corresponds to involvement in the event, and a
setting of 0 corresponds to no involvement. When new data is
available, these bits are not cleared but are overwritten by the
new data. The TAP_SIGN register should be read before clearing
the interrupt. Disabling an axis from participation clears the
corresponding source bit when the next single-tap/double-tap
event occurs.
Register 0x3B—ORIENT_CONF (Read/Write)
D7
INT_
ORIENT
INT_ORIENT Bit
Setting the INT_ORIENT bit enables the orientation interrupt.
A value of 1 overrides the overrun function of the device and
replaces overrun in the INT_MAP (Address 0x2F), INT_ENABLE
(Address 0x2E), and INT_SOURCE (Address 0x30) registers with
the orientation function. After setting the INT_ORIENT bit, the
orientation bits in the INT_MAP and INT_ENABLE registers must
be configured to map the orientation interrupt to INT1 or INT2
and to enable generation of the interrupt to the pin.
D6
XSIGN
D6
D6
0
Dead zone
D5
YSIGN
D5
D5
D4
ZSIGN
D4
D4
D3
INT_
3D
D3
0
D3
Entries
D2
D2
XTAP
D2
Divisor
D1
D1
YTAP
D1
D0
ZTAP
D0
D0
Rev. A | Page 27 of 40
An orientation interrupt is generated whenever the orientation
status for the mode selected by the INT_3D bit changes in the
orient register (Address 0x3C). The orientation interrupt is
cleared by reading the INT_SOURCE register. Clearing the
INT_ORIENT bit, or the orientation bit in the INT_ENABLE
register (Address 0x2E), disables and clears the interrupt.
Writing to the BW_RATE register (Address 0x2C) or placing
the part into standby mode resets the orientation feature, clearing
the orientation filter and the interrupt. However, resetting the
orientation feature also resets the orientation status in the orient
register (Address 0x3C) and, therefore, causes an interrupt to be
generated when the next output sample is available if the present
orientation is not the default orientation. A value of 0 for the
INT_ORIENT bit disables generation of the orientation interrupt
and permits the use of the overrun function.
Dead Zone Bits
These bits determine the region between two adjacent orientations,
where the orientation is considered invalid and is not updated. A
value of 0 may result in undesirable behavior when the orientation
is close to the bisector between two adjacent regions. The dead zone
angle is determined by these bits, as described in Table 24. See the
Orientation Sensing section for more details.
Table 24. Dead Zone and Divisor Codes
Decimal
0
1
2
3
4
5
6
7
INT_3D Bit
If the orientation interrupt is enabled, the INT_3D bit determines
whether 2D or 3D orientation detection generates an interrupt.
A value of 0 generates an interrupt only if the 2D orientation
changes from a valid 2D orientation to a different valid 2D
orientation. A value of 1 generates an interrupt only if the 3D
orientation changes from a valid 3D orientation to a different
valid 3D orientation.
Divisor Bits
These bits set the bandwidth of the filter used to low-pass filter the
measured acceleration for stable orientation sensing. The divisor
bandwidth is determined by these bits, as detailed in Table 24,
where ODR is the output data rate set in the BW_RATE register
(Address 0x2C). See the Orientation Sensing section for more
details.
Binary
000
001
010
011
100
101
110
111
Dead Zone Angle
(Degrees)
5.1
10.2
15.2
20.4
25.5
30.8
36.1
41.4
Divisor
Bandwidth (Hz)
ODR/9
ODR/22
ODR/50
ODR/100
ODR/200
ODR/400
ODR/800
ODR/1600
ADXL346

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