AS1158 austriamicrosystems, AS1158 Datasheet
AS1158
Specifications of AS1158
Related parts for AS1158
AS1158 Summary of contents
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... PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The devices are available in a 8-pin SOIC package. Figure 1. AS1153, AS1157 - Block Diagram www.austriamicrosystems.com/Interfaces-LVDS/AS1153 2 Key Features Flow-Through Pinout Guaranteed 260Mbps Data Rate 300ps Pulse Skew (Max) Conform to ANSI TIA/EIA-644 LVDS Standards Single +3 ...
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... Noninverting Differential Receiver Input Noninverting Differential Receiver Input 3 IN2+ Inverting Differential Receiver Input 4 IN2- Ground 5 GND LVCMOS/LVTTL Receiver Output 6 OUT2 LVCMOS/LVTTL Receiver Output 7 OUT1 Power-Supply Input. Bypass V 8 VCC www.austriamicrosystems.com/Interfaces-LVDS/AS1153 IN1- 1 VCC 8 IN1+ OUT1 2 7 AS1153/57 IN2+ 3 OUT2 6 IN2- 4 GND 5 Description to GND with 0.1µ ...
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... INx+, INx- to GND OUTx+, OUTx- to GND Electrostatic Discharge Electrostatic Discharge HBM Temperature Ranges and Storage Conditions Thermal Resistance Θ JA Junction Temperature Storage Temperature Range Package Body Temperature Humidity non-condensing Moisture Sensitive Level www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Min Max Units -0.3 5.0 V -0.3 5.0 V -0.3 Vcc + 0.3 ...
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... Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note: All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. www.austriamicrosystems.com/Interfaces-LVDS/AS1153 | = +0.1 to +1.0V, Common-Mode Voltage +3.3V +25º ...
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... VOH = +1.3V d. VOL = +1.1V 8. Output criteria: a. Duty cycle = 60 0.4V (max 2.7V (min Load = 10pF www.austriamicrosystems.com/Interfaces-LVDS/AS1153 | = 0.2 to 1.0V, Common-Mode Voltage -40 to +85ºC. Typical values are at V AMB Symbol Conditions Figure 20 on page 11 and Figure PHLD page 12 Figure 20 on page 11 and Figure 21 on ...
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... Supply Voltage (V) Figure 7. Output Low Voltage vs 74,5 74 73 3,1 3,2 3,3 3,4 Supply Voltage (V) www.austriamicrosystems.com/Interfaces-LVDS/AS1153 = 10pF +25ºC, unless otherwise noted. AMB Figure 4. Supply Current vs. Temperature -45 -30 -15 250 300 Figure 6. Output Short-Circuit Current vs. V 120 100 3.5 3 ...
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... Common-Mode Voltage(V) Figure 13. Differential Propagation Delay vs. Load 3 2.5 t PHLD 2 t PLHD 1 Capacitive Load (pF) www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Figure 10. Differential Propagation Delay vs. Temp. 2.05 2 1.95 1.9 1.85 1.8 1.75 3.5 3.6 -45 -30 -15 0 Figure 12. Differential Propagation Delay vs 2.25 2 1.75 1.5 1. ...
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... Figure 16. Transition Time vs 400 390 380 t THL 370 t TLH 360 350 340 3 3.1 3.2 3.3 3.4 Supply Voltage(V) www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Figure 15. Transition Time vs. Capacitive Load 1600 1400 1200 1000 800 600 400 3.5 3 Capacitive Load (pF) Figure 17. Transition Time vs. Temperature 475 450 425 ...
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... Failsafe circuit and thus forcing the device output high. CC Figure 18. Failsafe Input Circuit IN2 V - 0.3V CC INx+ R IN1 R IN1 INx- AS1153 www.austriamicrosystems.com/Interfaces-LVDS/AS1153 - 0.3V (nominal). If the input is driven CC - 0.3V and the Failsafe circuit is not activated. If the IN2 V - 0.3V CC INx+ R IN1 R DIFF ...
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... Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential impedance. Avoid 90° turns (use two 45° turns). Minimize the number of vias to further prevent impedance irregularities. www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Output OUTx H ...
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... Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Propagation Delay and Transition Time Test Circuit www.austriamicrosystems.com/Interfaces-LVDS/AS1153 INx+ Pulse ...
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... AS1153, AS1157 Datasheet - Figure 21. Propagation Delay and Transition Time Waveforms INx- V INx Note IN- IN+ 2 20% OUTx www.austriamicrosystems.com/Interfaces-LVDS/AS1153 PLHD 80% 50% t TLH Revision 1. PHLD V OH 80% 50% 20 THL ...
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... AS1153, AS1157 Datasheet - Package Drawings and Markings Figure 22. 8-pin SOIC Marking Table 6. Packaging Code xxxx xxxx encoded Datecode www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Revision 1. ...
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... AS1153, AS1157 Datasheet - Figure 23. 8-pin SOIC Package Diagram www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Revision 1. ...
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... Description Dual LVDS Receiver Dual LVDS Receiver Dual LVDS Receiver, with termination Dual LVDS Receiver, with termination http://www.austriamicrosystems.com/ICdirect mailto:sales@austriamicrosystems.com Revision 1.02 Delivery Form Package Tubes 8-pin SOIC Tape and Reel 8-pin SOIC Tubes ...
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... AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application ...