PIC18F4423-E/ML Microchip Technology, PIC18F4423-E/ML Datasheet - Page 15
![16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4423-E/ML
Manufacturer Part Number
PIC18F4423-E/ML
Description
16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
Specifications of PIC18F4423-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.2.1
The previous programming example assumed that the
device had been Bulk Erased prior to programming
(see Section 3.1.1 “High-Voltage ICSP Bulk Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
TABLE 3-6:
© 2005 Microchip Technology Inc.
Step 1: Direct access to code memory.
Step 2: Read and modify code memory (see Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”).
Step 3: Set the Table Pointer for the block to be erased.
Step 4: Enable memory writes and setup an erase.
Step 5: Initiate erase.
Step 6: Load write buffer. The correct bytes will be selected based on the Table Pointer.
To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes
(see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of
the erase buffer.
Step 7: Disable writes.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
0000
4-Bit
.
.
.
MODIFYING CODE MEMORY
8E A6
9C A6
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
84 A6
88 A6
82 A6
00 00
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
94 A6
MODIFYING CODE MEMORY
Data Payload
.
.
.
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
NOP - hold PGC high for time P9 and low for time P10.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2 bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
BCF
PIC18F2423/2523/4423/4523
EECON1, EEPGD
EECON1, CFGS
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
EECON1, FREE
EECON1, WR
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
The appropriate number of bytes required for the erase
buffer must be read out of code memory (as described
in Section 4.2 “Verify Code Memory and ID
Locations”) and buffered. Modifications can be made
on this buffer. Then, the block of code memory that was
read out must be erased and rewritten with the
modified data.
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
Core Instruction
DS39759A-page 15