DSPIC30F4012-20E/ML Microchip Technology, DSPIC30F4012-20E/ML Datasheet - Page 146
DSPIC30F4012-20E/ML
Manufacturer Part Number
DSPIC30F4012-20E/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4012-20E/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
20
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F401220EML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4012-20E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F4012-30ISO PDF datasheet #2
- DSPIC30F4012-30ISO PDF datasheet #3
- DSPIC30F4012-30ISO PDF datasheet #4
- DSPIC30F4012-30ISO PDF datasheet #5
- DSPIC30F4012-30ISO PDF datasheet #6
- Current page: 146 of 238
- Download datasheet (4Mb)
combine to directly affect the time required to charge the
dsPIC30F4011/4012
20.8
The analog input model of the 10-bit ADC is shown in
Figure
function of the internal amplifier settling time, device
V
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
capacitor C
log sources must therefore be small enough to fully
charge the holding capacitor within the chosen sample
time. To minimize the effects of pin leakage currents on
the accuracy of the ADC, the maximum recommended
source impedance, R
channel is selected (changed), this sampling function
must be completed prior to starting the conversion. The
internal holding capacitor will be in a discharged state
prior to each sample operation.
FIGURE 20-3:
DS70135G-page 146
DD
IC
) and the internal sampling switch (R
and the holding capacitor charge time.
20-3. The total sampling time for the ADC is a
A/D Acquisition Requirements
HOLD
Note: C
. The combined impedance of the ana-
Legend: C
VA
HOLD
S
Rs
PIN
S
, is 5 kΩ. After the analog input
A/D CONVERTER ANALOG INPUT MODEL
), the interconnect impedance
value depends on device package and is not tested. Effect of C
V
I leakage
R
R
C
) must be allowed to fully
ANx
PIN
T
IC
SS
HOLD
C
PIN
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
SS
) impedance
V
DD
V
V
T
T
= 0.6V
= 0.6V
R
I
±500 nA
LEAKAGE
IC
≤ 250Ω
The user must allow at least 1 T
time, T
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the ADC. In an
automatic configuration, the user must allow enough
time between conversion triggers so that the minimum
sample time can be satisfied. Refer to
“Electrical Characteristics”
requirements.
SAMP
Sampling
Switch
R
, between conversions to allow each sam-
SS
PIN
R
SS
V
negligible if Rs ≤ 5 kΩ.
SS
C
= DAC Capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
© 2010 Microchip Technology Inc.
for T
AD
AD
period of sampling
and sample time
Section 24.0
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