DSPIC30F1010-20E/MM Microchip Technology, DSPIC30F1010-20E/MM Datasheet - Page 217
DSPIC30F1010-20E/MM
Manufacturer Part Number
DSPIC30F1010-20E/MM
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F1010-20E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCK
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 217 of 286
- Download datasheet (5Mb)
18.9.2
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module
that allows them to operate during Idle.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• on any interrupt that is individually enabled (IE bit
• on any Reset (POR, MCLR)
• on WDT time-out
Upon wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle status bit in
RCON register is set upon wake-up.
Any Reset, other than POR, will set the Idle status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
© 2006 Microchip Technology Inc.
is ‘1’) and meets the required priority level
IDLE MODE
Preliminary
18.10 Device Configuration Registers
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are six
Configuration registers available to the user:
1.
2.
3.
4.
5.
6.
The placement of the Configuration bits is automati-
cally handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For addi-
tional information, please refer to the programming
specifications of the device.
Table 18-5 shows the bit descriptions of the FGS and
FBS registers for the dsPIC30F1010. Table 18-6
shows the bit descriptions of the FGS and FBS regis-
ters for dsPIC30F202x devices. Table 18-7 shows the
bit descriptions of FWDT and the FPOR registers for
dsPIC30F1010/202X devices.
Note:
dsPIC30F1010/202X
FBS (0xF80000): Boot Code Segment
Configuration Register
FGS (0xF80004): General Code Segment
Configuration Register
FOSCEL (0xF80006): Oscillator Selection
Configuration Register
FOSC (0xF80008): Oscillator Configuration
Register
FWDT (0xF8000A): Watchdog Timer
Configuration Register
FPOR (0xF8000C): Power-On Reset
Configuration Register
If the code protection configuration fuse
bits (GSS<1:0> and GWRP in the FGS
register) have been programmed, an
erase of the entire code-protected device
is only possible at voltages V
DS70178C-page 215
DD
4.5V.
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